A method of forming a stacked image sensor comprises providing a first substrate and a second substrate. The first substrate comprises a first matrix comprising first quantum dots, a first dielectric layer adjacent to the first matrix, and first bond pads disposed in the first dielectric layer. The second substrate comprises a second matrix comprising second quantum dots, a second dielectric layer adjacent to the second matrix, and second bond pads disposed in the second dielectric layer. The method includes hybrid bonding the first substrate to the second substrate without use of an intervening adhesive to form the stacked image sensor, where the hybrid bonding connects the first bond pads to the second bond pads.

A method of forming a stacked image sensor comprises providing a first substrate and a second substrate. The first substrate comprises a first matrix comprising first quantum dots, a first dielectric layer adjacent to the first matrix, and first bond pads disposed in the first dielectric layer. The second substrate comprises a second matrix comprising second quantum dots, a second dielectric layer adjacent to the second matrix, and second bond pads disposed in the second dielectric layer. The method includes hybrid bonding the first substrate to the second substrate without use of an intervening adhesive to form the stacked image sensor, where the hybrid bonding connects the first bond pads to the second bond pads.

Multi-chip image sensor semiconductor packages and methods for forming such packages are disclosed. A multi-chip package includes at least one cover covering a sensor die. Some multi-chip packages include multiple covers for covering each sensor die. In one multi-chip packages, a single cover covers multiple sensor chips.

Multi-chip image sensor semiconductor packages and methods for forming such packages are disclosed. A multi-chip package includes at least one cover covering a sensor die. Some multi-chip packages include multiple covers for covering each sensor die. In one multi-chip packages, a single cover covers multiple sensor chips.

A power module according to the present disclosure comprises: a circuit board disposed on a main surface of a base plate; a main terminal part capable of inputting power to a circuit pattern of the circuit board; an output terminal part capable of outputting the power converted by a power semiconductor element connected to the circuit pattern; a case having a side wall part that while being disposed on the main surface, surrounds the circuit board in a main surface-widening direction to define a housing space for housing the circuit board, and a lid part that is disposed on the side wall part to close off the housing space, thereby blocking off the inside of the housing space; an insulating part disposed inside the housing space to bury the circuit board; and an optical detection part disposed in the case and capable of detecting the light generated inside the housing space due to the entrance of the light from a distal end surface. A plurality of distal end surfaces of the optical detection part are arranged side by side along a side edge part of the circuit pattern opposed to an inner surface of the side wall part in the housing space so that an optical detection range includes the side edge part.

A power module according to the present disclosure comprises: a circuit board disposed on a main surface of a base plate; a main terminal part capable of inputting power to a circuit pattern of the circuit board; an output terminal part capable of outputting the power converted by a power semiconductor element connected to the circuit pattern; a case having a side wall part that while being disposed on the main surface, surrounds the circuit board in a main surface-widening direction to define a housing space for housing the circuit board, and a lid part that is disposed on the side wall part to close off the housing space, thereby blocking off the inside of the housing space; an insulating part disposed inside the housing space to bury the circuit board; and an optical detection part disposed in the case and capable of detecting the light generated inside the housing space due to the entrance of the light from a distal end surface. A plurality of distal end surfaces of the optical detection part are arranged side by side along a side edge part of the circuit pattern opposed to an inner surface of the side wall part in the housing space so that an optical detection range includes the side edge part.

Provided is a semiconductor device (10) including a stack of a first semiconductor substrate (100) and a second semiconductor substrate (200), in which the first semiconductor substrate includes an imaging element (300) that generates a charge in response to light from a light incident surface of the first semiconductor substrate and a first memory element (400) provided on a side opposite to the light incident surface with respect to the imaging element, and the first memory element has a stacked structure in which a magnetization fixed layer (402), a nonmagnetic layer (404), and a storage layer (406) are stacked in the order mentioned from the light incident surface side.

Provided is a semiconductor device (10) including a stack of a first semiconductor substrate (100) and a second semiconductor substrate (200), in which the first semiconductor substrate includes an imaging element (300) that generates a charge in response to light from a light incident surface of the first semiconductor substrate and a first memory element (400) provided on a side opposite to the light incident surface with respect to the imaging element, and the first memory element has a stacked structure in which a magnetization fixed layer (402), a nonmagnetic layer (404), and a storage layer (406) are stacked in the order mentioned from the light incident surface side.

Detecting defective joining parts between semiconductor substrates is disclosed. In one example, a semiconductor device includes a first semiconductor substrate and a second semiconductor substrate stacked and joined together, a connection line having a plurality of pairs of connection pads connected to each other with a joint surface between the substrates interposed therebetween, the connection line being routed from one of the first and second semiconductor substrates to the other alternately a plurality of times via the pairs of the connection pads, and a detection circuit configured to detect whether or not the connection line has failed.

A method produces a microelectronics device by hybrid bonding of individual chips onto a handle wafer, of the Die-to-Wafer type, includes a flow protocol for thinning the rear substrate of the chips. The flow protocol includes a pre-thinning grinding of the rear substrate of the individual chips once they have been attached to the wafer. This grinding is preceded by the formation of a protective layer protecting the trenches formed by the spaces between the attached individual chips. Next, a rectification etching rectifies the height of the rear substrate of each of the attached individual chips, via chemical wet etching, to eliminate the Total Thickness Variation. This etching is selective with respect to an etch-stop element contained in the respective substrates of the attached chips and which is used to stop the etching at a level that is substantially uniform for each of the chips.