A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. Luminescent ceramic layers according to embodiments of the invention may be more robust and less sensitive to temperature than prior art phosphor layers. In addition, luminescent ceramics may exhibit less scattering and may therefore increase the conversion efficiency over prior art phosphor layers.

A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer. First and second electrically conductive tile micro-wires and first and second conductive tile contact pads are electrically connected to the first and second tile micro-wires, respectively. The light emitter includes a plurality of semiconductor layers and the first and second electrodes are disposed on a common side of the semiconductor layers opposite the emitter side of the tile layer. The first and second tile micro-wires and first and second tile contact pads are disposed on the backplane side of the tile layer.

An active-matrix touchscreen includes a substrate, a system controller, and a plurality of spatially separated independent touch elements disposed on the substrate. Each touch element includes a touch sensor and a touch controller circuit that provides one or more sensor-control signals to the touch sensor and receives a sense signal responsive to the sensor-control signals from the touch sensor. Each touch sensor operates independently of any other touch sensor.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer. First and second electrically conductive tile micro-wires and first and second conductive tile contact pads are electrically connected to the first and second tile micro-wires, respectively. The light emitter includes a plurality of semiconductor layers and the first and second electrodes are disposed on a common side of the semiconductor layers opposite the emitter side of the tile layer. The first and second tile micro-wires and first and second tile contact pads are disposed on the backplane side of the tile layer.

The invention relates to a method of manufacturing optoelectronic devices including light-emitting diodes, including the steps of: a) forming a first integrated circuit chip including light-emitting diodes; b) bonding a second integrated chip to a first surface of the first chip; c) decreasing the thickness of the first chip on the side opposite to the first surface to form a second surface opposite to the first surface; d) bonding, to the second surface, a cap including a silicon wafer provided with recesses opposite the light-emitting diodes; e) decreasing the thickness of the second chip; f) decreasing the thickness of the silicon wafer before step d) or after step e), each recess being filled with a photoluminescent material; and g) sawing the structure obtained at step f) into a plurality of separate optoelectronic devices.

A method for manufacturing a high voltage LED flip chip is provided, including: providing a substrate; forming an epitaxy stacking layer on the substrate; etching the epitaxy stacking layer to form a first groove and a Mesa-platform on each chip-unit region; forming a first electrode on each of the Mesa-platforms, wherein the first electrodes on two neighboring chip-unit regions form a second groove; forming a first insulation layer covering the Mesa-platforms and the first electrodes, filling the second groove and partially filling the first grooves to form a third groove; etching the first insulation layer to form fourth groove; and forming an interconnection electrode, wherein the interconnection electrode fills the third groove and the fourth groove, two neighboring interconnection electrodes form a fifth groove, the interconnection electrode connects the first electrode on one chip-unit region and the first semiconductor layer on the other chip-unit region. LED formed has improved performance.

Standardized photon building blocks are packaged in molded interconnect structures to form a variety of LED array products. No electrical conductors pass between the top and bottom surfaces of the substrate upon which LED dies are mounted. Microdots of highly reflective material are jetted onto the top surface. Landing pads on the top surface of the substrate are attached to contact pads disposed on the underside of a lip of the interconnect structure. In a solder reflow process, the photon building blocks self-align within the interconnect structure. Conductors in the interconnect structure are electrically coupled to the LED dies in the photon building blocks through the contact pads and landing pads. Compression molding is used to form lenses over the LED dies and leaves a flash layer of silicone covering the landing pads. The flash layer laterally above the landing pads is removed by blasting particles at the flash layer.

A protective covering configured for use with a mobile electronics device, including a front wall and a plurality of side walls defining a primary cavity. A back wall is disposed within the primary cavity separating the primary cavity into a protective covering electronics housing cavity and a mobile electronic device housing cavity. One or more apertures are disposed within the front wall. A light source is disposed within the protective covering electronics housing cavity, wherein at least a portion of the light source is disposed outside of the protective covering electronics housing cavity and through at least one of the one or more apertures in the front wall. A heat sink is disposed within the protective covering electronics housing cavity and in contact with the light source.

A heat sink for an illumination device may include at least one heat sink portion which includes heat-conducting plastic. At least one metallic heat sink portion is at least partially embedded in the plastic material of the heat-conducting plastic.