A display device includes: a first inorganic insulating layer; a wiring disposed on the first inorganic insulating layer; a second inorganic insulating layer covering the wiring; and a display element disposed on the second inorganic insulating layer, wherein the wiring includes a lower layer including at least one of aluminum and an aluminum alloy, an upper layer disposed on the lower layer and including at least one of titanium and titanium oxide, and an intermediate layer disposed between the lower layer and the upper layer and including titanium aluminide.

Provided is a display device having defined therein an opening corresponding to a boundary region, and including a plurality of insulating layers disposed on a base layer, an organic layer disposed in the opening, a first connection electrode disposed on the uppermost insulating layer among the plurality of insulating layers, connected to a first signal line through a first contact hole passing through the organic layer, and connected to a transistor through a second contact hole passing through corresponding insulating layers among the plurality of insulating layers, and a second signal line disposed on a layer different from a layer on which the first line is disposed.

A display device includes a first active pattern, a second active pattern spaced apart from the first active pattern in a plan view, a first connection pattern contacting the first active pattern, a second connection pattern contacting the second active pattern, a first pixel electrode, a second pixel electrode spaced apart from the first pixel electrode in the plan view, a common voltage pattern including a first protrusion portion protruding from a line portion in the plan view and overlapping the second connection pattern in a cross-sectional view, an emission layer disposed on the common voltage pattern, and a common electrode connecting the common voltage pattern.

A display device includes a substrate provided with a plurality of pixels, a circuit element layer provided on the substrate and provided with an auxiliary electrode, an insulating layer provided on the circuit element layer and provided with a plurality of connection electrodes spaced apart from one another and a first trench, a fence structure provided on the plurality of connection electrodes, an organic light emitting layer provided on the fence structure, and a second electrode arranged on the organic light emitting layer, wherein the plurality of connection electrodes are electrically connected with the auxiliary electrode, at least one of the plurality of connection electrodes is exposed from the first trench, and the second electrode is in contact with a connection electrode exposed from the first trench. Therefore, a luminance difference between an outer portion of a panel and a center portion of the panel may be reduced.

A display panel includes a base layer, a signal line which is disposed on the base layer and includes a first layer including aluminum and a second layer disposed directly on the first layer and consisting of niobium, a first thin film transistor connected to the signal line, a second thin film transistor disposed on the base layer, a capacitor electrically connected to the second thin film transistor, and a light emitting element electrically connected to the second thin film transistor.

An opto-electronic device includes: (1) a substrate including a first region and a second region; and (2) a conductive coating covering the second region of the substrate. The first region of the substrate is exposed from the conductive coating, and an edge the conductive coating adjacent to the first region of the substrate has a contact angle that is greater than about 20 degrees.

A display device and electronic device are disclosed. In one example, a display device includes a pixel array portion including pixels arrayed in a matrix having a row direction and a column direction. The pixels each respectively including a light emission unit. A fixed potential line surrounds the pixel array portion in a frame portion outside the pixel array portion, and a pixel portion auxiliary cable is arranged to extend across the pixel array portion. The pixel portion auxiliary cable is interlayer connected to the fixed potential line at a location in the frame portion outside the pixel array portion.

A transparent display panel and a transparent display device including the same are disclosed. In a transparent display panel, a VSS voltage line does not surround an outer periphery of a display region. Rather, upper and lower VSS voltage lines respectively disposed on upper and lower sides to the display region are electrically connected to each other via at least one VSS voltage connection line extending across the display region. Thus, left and right non-transparent and thick VSS voltage lines disposed on the left and right sides to the display region may be omitted. Thus, a transparent region of the transparent display panel and a bezel of a transparent display device may be increased or maximized or the bezel thereof may be made slim.

In a transparent display panel, a layer of each of a VSS voltage connection line and a VDD voltage connection line as a power line in a display region is different from a layer of a data line and a reference voltage connection line, while each of the VSS voltage connection line and the VDD voltage connection line partially overlaps the data line and the reference voltage connection line. Thus, an overall width of a line region may be reduced. Thus, an area of a pixel circuit region is reduced, such that an area of a transmissive region increases, thereby to increase an overall transmittance of the panel. Further, a width of each of the VSS voltage connection line and the VDD voltage connection line is large while reducing or minimizing an area of the line region in the display region. This reduces or minimizes occurrence of VDD drop or VSS rise, thereby to reduce luminance non-uniformity of the panel.

A display device includes a base substrate including a first substrate and a second substrate sequentially laminated, a lower semiconductor layer disposed on at least one of the first substrate and the second substrate, a buffer layer disposed on the base substrate, an active semiconductor layer disposed on the buffer layer and including a first active layer of a first transistor and a second active layer of a second transistor, a first insulating layer disposed on the active semiconductor layer, and a first conductive layer disposed on the first insulating layer and including a first gate electrode of the first transistor and a second gate electrode of the second transistor, wherein the lower semiconductor layer overlaps the first active layer, and does not overlap the second active layer.