The present application provides display panels, transparent display panels and manufacturing methods therefor. A transparent display panel includes a light transmitting substrate, pixel structures, second electrode connecting portions, and a nano-material layer. A display region of the light transmitting substrate includes alternately distributed pixel regions and non-pixel regions. The pixel structures are located in the pixel regions, each including: a first electrode close to the light transmitting substrate, a second electrode away from the light transmitting substrate, and a light emitting block between the first electrode and the second electrode. The second electrode connecting portions are located in the non-pixel regions, and connect adjacent second electrodes, and one or more materials for the second electrode connecting portions are the same as the one or more materials for the second electrodes, both including transflective materials. The nano-material layer includes a plurality of nano-island structures separated from each other, and is located at least on a side of the second electrode connecting portions away from the light transmitting substrate, and is configured to excite surface plasma polaritons corresponding to infrared light and scatter the infrared light.

The present disclosure relates to a display panel and a repair method thereof. The display panel includes a plurality of pixel circuits in which an emission region, through which light from a light-emitting element is emitted, is defined, a power line configured to apply a pixel driving voltage to the pixel circuits, a reference voltage line to which a reference voltage lower than the pixel driving voltage is applied, and a branch line connected to the reference voltage line to apply the reference voltage to one or more of the pixel circuits. At least a portion of the branch line includes a partially metalized semiconductor layer.

A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, the second connection pads spaced apart from the first connection pads in a second direction perpendicular to the first direction, and a driving chip disposed on the board between the first connection pads and the second connection pads. Each of the first connection pads includes a first conductive layer disposed on the board, a second conductive layer which entirely overlaps with the first conductive layer in a plan view, is disposed on the first conductive layer and is formed of a different material from that of the first conductive layer, and a third conductive layer entirely overlapping with the second conductive layer and disposed on the second conductive layer.

A transparent display panel and a transparent display device including the same are disclosed. In a transparent display panel, a VSS voltage line does not surround an outer periphery of a display region. Rather, upper and lower VSS voltage lines respectively disposed on upper and lower sides to the display region are electrically connected to each other via at least one VSS voltage connection line extending across the display region. Thus, left and right non-transparent and thick VSS voltage lines disposed on the left and right sides to the display region may be omitted. Thus, a transparent region of the transparent display panel and a bezel of a transparent display device may be increased or maximized or the bezel thereof may be made slim.

The present application provides a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate, and a light-emitting layer disposed on the driving circuit layer. The driving circuit layer includes a first metal layer, the first metal layer includes a first metal trace, the light-emitting layer includes multiple light-emitting portions, and a vertical distance between an orthographic projection of a center of each light-emitting portion projected on the first metal layer and a symmetry axis of the first metal trace is less than or equal to 5 μm.

A display device including: a substrate including a main area and a sub-area at a side of the main area; a thin-film transistor on the substrate and positioned in the main area; a first insulating layer on a gate electrode of the thin-film transistor; a light-emitting element on the first insulating layer, positioned in the main area, and electrically connected to the thin-film transistor; a plurality of pads on the first insulating layer and positioned in the sub-area; and a light-blocking layer overlapping the plurality of pads and located between the substrate and the first insulating layer.

A display device includes a scan write line configured to receive a scan write signal, a scan initialization line configured to receive a scan initialization signal, a sweep signal line configured to receive a sweep signal, a first data line configured to receive a first data voltage, a second data line configured to receive a second data voltage, and a subpixel connected to the scan write line, the scan initialization line, the sweep signal line, the first data line, and the second data line. The subpixel includes a light-emitting element, a first pixel driver including a first transistor configured to generate a control current according to the first data voltage of the first data line, and a second pixel driver including an eighth transistor configured to generate a driving current applied to the light-emitting element according to the second data voltage.

The present disclosure relates to a display panel, a display device and a manufacturing method of a display panel. The display panel includes: a display substrate having a display area and a non-display area, the display substrate including a substrate and an IC bonding portion which includes: a pin; a first passivation layer located on one side of the substrate adjacent to the pin and covering a peripheral area of the pin, and exposing a central area of the pin; a first barrier layer located on one side of the first passivation layer away from the substrate and covered at the first passivation layer and an edge of the first passivation layer connected to the pin; and a first metal layer located on one side of the first barrier layer away from the substrate, at least covering a central portion of the pin, and electrically connected to the pin.

Disclosed is a light emitting display device configured such that a power line that supplies source voltage from a pad unit and a cathode are connected to each other using a trench provided in a planarization layer so as to have a linear shape, whereby reliability in prevention of permeation is improved, an area that protrudes and is processed for a connection portion is minimized, whereby a non-display area is reduced, a cathode connection portion is located in a wide area to increase a heat generation path, whereby reliability is improved.

A display comprises a substrate (e.g., glass), a plurality of pixel circuits disposed on a back surface of the substrate, and a plurality of self-emitting devices disposed on a front surface of the substrate. The self-emitting devices are electrically connected to the plurality of pixel circuits by at least one electrically conductive via traveling through the substrate. Each pixel circuit comprises a first and a second transistor and a capacitor. The self-emitting devices may be LEDs or OLEDs for example.