A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.

A spin element includes a wiring, a laminated body including a first ferromagnetic layer laminated on the wiring, a first conductive part and a second conductive part which sandwich the first ferromagnetic layer in a plan view in a laminating direction, and a first high resistance layer which is in contact with the wiring between the first conductive part and the wiring and has an electrical resistivity equal to or higher than that of the wiring.

The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A new structure of the SOT channel has one or more magnetic insertion layers superposed or stacked with one or more heavy metal layer(s). Through proximity to a magnetic insertion layer, a surface portion of a heavy metal layer is magnetized to include a magnetization. The magnetization within the heavy metal layer enhances spin-dependent scattering, which leads to increased transverse spin imbalance.

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.

Switchable antiferromagnetic (AFM) memory devices are provided based on an active material, Fe.sub.xNbS.sub.2, where x>1/3 and Fe.sub.xNbS.sub.2 where x<1/3, that exhibits the ability to manipulate spin information “non-locally” i.e. tens of microns away from the electrical stimulus. Spin information can be transported and stored non-locally in the Fe.sub.xNbS.sub.2 material. The devices leverage two long range effects: collective excitations to carry spin and strong magnetoelastic coupling to allow complex domain structures to propagate over large distances. The application of current pulses across the material can rotate or switch the AFM order between multiple directions. Non-local resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.

Switchable antiferromagnetic (AFM) memory devices are provided based on an active material, Fe.sub.xNbS.sub.2, where x>1/3 and Fe.sub.xNbS.sub.2 where x<1/3, that exhibits the ability to manipulate spin information “non-locally” i.e. tens of microns away from the electrical stimulus. Spin information can be transported and stored non-locally in the Fe.sub.xNbS.sub.2 material. The devices leverage two long range effects: collective excitations to carry spin and strong magnetoelastic coupling to allow complex domain structures to propagate over large distances. The application of current pulses across the material can rotate or switch the AFM order between multiple directions. Non-local resistance measurements can detect the orientation of the AFM order as high or low resistance states. The state of the device can be set by input current pulses, and read-out by the resistance measurement, forming a non-volatile, AFM memory storage bit.