A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, and a reference layer, forming a cylindrical diode structure above and in electrical contact with the SOT-MRAM cell stack, forming a write line disposed in electrical contact with the SHE rail, and forming a read line disposed above and adjacent to an outer cylindrical electrode of the diode structure.

The present disclosure relates to a magnetic memory structure with a voltage-controlled gain-cell configuration, which includes a memory resistive device, a first transistor connected in series with the memory resistive device, and a second transistor. The memory resistive device has a baseline resistance larger than 10 MΩ, and is eligible to exhibit a ‘1’ state and a ‘0’ state and exhibit a resistance change between the ‘1’ state and the ‘0’ state. The second transistor has a gate connected to a connection node of the first transistor and the memory resistive device. When the memory resistive device exhibits the ‘1’ state, a gate voltage for the second transistor is smaller than a threshold voltage of the second transistor, and when the memory resistive device exhibits the ‘0’ state, the gate voltage for the second transistor is larger than the threshold voltage of the second transistor.

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a spin-Hall-effect (SHE) layer above and in electrical contact with a transistor, forming a spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) cell stack disposed above and in electrical contact with the SHE rail, wherein the SOT-MRAM cell stack comprises a free layer, a tunnel junction layer, a reference layer, and a diode structure, forming a write line disposed in electrical contact with the SHE rail, forming a protective dielectric layer covering a portion of the SOT-MRAM cell stack, and forming a read line disposed above and adjacent to the diode structure.

Provided are magnetoresistance effect element and a Heusler alloy in which an amount of energy required to rotate magnetization can be reduced. The magnetoresistance effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a non-magnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, in which at least one of the first ferromagnetic layer and the second ferromagnetic layer is a Heusler alloy in which a portion of elements of an alloy represented by Co.sub.2Fe.sub.αZ.sub.β is substituted with a substitution element, in which Z is one or more elements selected from the group consisting of Mn, Cr, Al, Si, Ga, Ge, and Sn, α and β satisfy 2.3≤α+β, α<β, and 0.5<α<1.9, and the substitution element is an element different from the Z element and has a smaller magnetic moment than Co.

A memory structure, device, and method of making the same, the memory structure including a surrounding gate thin film transistor (TFT) and a memory cell stacked on the GAA transistor. The GAA transistor includes: a channel comprising a semiconductor material; a source electrode electrically connected to a first end of the channel; a drain electrode electrically connected to an opposing second end of the channel; a high-k dielectric layer surrounding the channel; and a gate electrode surrounding the high-k dielectric layer. The memory cell includes a first electrode that is electrically connected to the drain electrode.

A semiconductor structure includes an N.sup.th metal layer, a diffusion barrier layer over the N.sup.th metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1).sup.th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

A semiconductor structure includes an N.sup.th metal layer, a diffusion barrier layer over the N.sup.th metal layer, a first deposition of bottom electrode material over the diffusion barrier layer, a second deposition of bottom electrode material over the first deposition of bottom electrode material, a magnetic tunneling junction (MTJ) layer over the second deposition of bottom electrode material, a top electrode over the MTJ layer; and an (N+1).sup.th metal layer over the top electrode; wherein the diffusion barrier layer and the first deposition of bottom electrode material are laterally in contact with a dielectric layer, the first deposition of bottom electrode material spacing the diffusion barrier layer and the second deposition of bottom electrode material apart, and N is an integer greater than or equal to 1. An associated electrode structure and method are also disclosed.

An approach to provide a structure of a double magnetic tunnel junction device with two spacers that includes a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conduction layer, a first dielectric spacer on sides of the top magnetic tunnel junction stack and a portion of a top surface of the spin conduction layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel device includes the top magnetic tunnel junction stack with a width that is less than the width of the bottom magnetic tunnel junction stack.

Memory structures including an MTJ-containing pillar that is void of re-sputtered bottom electrode metal particles is provided by first forming the MTJ-containing pillar on a sacrificial material-containing structure, and thereafter replacing the sacrificial material-containing structure with at least a replacement bottom electrode structure. In some embodiments, the sacrificial material-containing structure is replaced with both a bottom electrode diffusion barrier liner and a replacement bottom electrode structure.