A circuit for sensing a current comprises a substrate having a first and a second major surface, the second major surface being opposite to the first major surface. At least one magnetic field sensing element is arranged on the first major surface of the substrate and is suitable for sensing a magnetic field caused by a current flow in a current conductor coupled to the second major surface. The substrate also comprises at least one insulation layer, substantially buried between the first major surface and the second major surface of the substrate.

A Hall effect sensor including a Hall element disposed at a surface of a semiconductor body, including a first doped region of a first conductivity type disposed over and abutted by an isolated second doped region of a second conductivity type. First through fourth terminals of the Hall element are in electrical contact with the first doped region, and a fifth terminal in electrical contact with the second doped region. A Hall effect sensor includes a first current source coupled to the first terminal of the Hall element, and common mode feedback regulation circuitry. The common mode feedback regulation circuitry has an output coupled to the third terminal and a ground node, and having an input coupled to the second and fourth terminals of the Hall element, and an output coupled to the third terminal and a ground node, where the second doped region is coupled to the third terminal.

A spin-orbit torque magnetoresistive random-access memory device formed by fabricating a plurality of stacks of vertical magnetoresistive random-access memory (MRAM) cell stacks, each stack formed upon a different bottom electrode, each stack including: a first vertical MRAM cell stack, the first vertical MRAM cell stack disposed upon a first bottom electrode, a first metal layer disposed above and in electrical contact with the first MRAM cell stack, and a second vertical MRAM cell stack, the second MRAM cell stack disposed above and in electrical contact with the first metal layer. Further by fabricating a low resistivity layer between adjacent stacks of vertical MRAM cell stacks, the low resistivity layer in electrical contact with the spin-Hall-Effect layer of each of the adjacent stacks.

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

The semiconductor device includes a magnetic switch provided to a semiconductor substrate. The magnetic switch includes: a horizontal Hall element including first electrodes and second electrodes arranged at positions perpendicular to the first electrodes; a switch circuit configured to select a drive current direction of the Hall element from four directions; an SH comparator configured to alternately perform a first operation for sampling a signal transmitted from the Hall element and a second operation for sending a signal which is based on a result of comparing a value of the sampled signal and a reference value; a latch circuit configured to hold this sent signal and send the held signal as a latch output signal; and a control circuit configured to select the drive current direction in each of a period for the first operation and a period for the second operation based on the latch output signal.

The present invention relates to a sensor device which has high S/N and excellent temperature characteristics. A sensor device has a semiconductor substrate, a first metal wiring layer provided on the semiconductor substrate, a first insulating layer provided on the first metal wiring layer, a compound semiconductor sensor element provided on the first insulating layer, a second metal wiring layer provided on the compound semiconductor sensor element and the first insulating layer, and a second insulating layer provided on the second metal wiring layer. A third insulating layer is provided between the first metal wiring layer and the second metal wiring layer, and the compound semiconductor sensor element is provided in the third insulating layer.

A sensor device comprising: a lead frame; a first/second semiconductor die having a first/second sensor structure at a first/second sensor location, and a plurality of first/second bond pads electrically connected to the lead frame; the semiconductor dies having a square or rectangular shape with a geometric center; the sensor locations are offset from the geometrical centers; the second die is stacked on top of the first die, and is rotated by a non-zero angle and optionally also offset or shifted with respect to the first die, such that a perpendicular projection of the first and second sensor location coincide.

A sensor cross-talk compensation system includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a vertical Hall sensor element disposed in the semiconductor substrate, the vertical Hall sensor element is configured to generate a sensor signal in response to a magnetic field impinging thereon; and an asymmetry detector configured to detect an asymmetric characteristic of the vertical Hall sensor element. The asymmetry detector includes a detector main region that vertically extends into the semiconductor substrate from the first main surface towards the second main surface and is of a conductivity type having a first doping concentration; and at least three detector contacts disposed in the detector main region at the first main surface, the at least three detector contacts are ohmic contacts of the conductivity type having a second doping concentration that is higher than the first doping concentration.

A memory device includes a spin-orbit-transfer (SOT) bottom electrode, an SOT ferromagnetic free layer, a first tunnel barrier layer, a spin-transfer-torque (STT) ferromagnetic free layer, a second tunnel barrier layer and a reference layer. The SOT ferromagnetic free layer is over the SOT bottom electrode. The SOT ferromagnetic free layer has a magnetic orientation switchable by the SOT bottom electrode using a spin Hall effect or Rashba effect. The first tunnel barrier layer is over the SOT ferromagnetic free layer. The STT ferromagnetic free layer is over the first tunnel barrier layer and has a magnetic orientation switchable using an STT effect. The second tunnel barrier layer is over the STT ferromagnetic free layer. The second tunnel barrier layer has a thickness different from a thickness of the first tunnel barrier layer. The reference layer is over the second tunnel barrier layer and has a fixed magnetic orientation.

A semiconductor device includes a semiconductor substrate of a first conductivity type, and a vertical Hall element provided on the semiconductor substrate. The vertical Hall element includes an impurity diffusion layer of a second conductivity type and three or more electrodes. The impurity diffusion layer is provided on the semiconductor substrate and has an impurity concentration which increases as a depth increases. The three or more electrodes are provided in a straight line on a surface of the impurity diffusion layer and are composed of an impurity region of the second conductivity type having a higher concentration than the impurity diffusion layer.