H10N60/01

PHONONIC MATERIAL AND METHOD FOR PRODUCING SAME
20230051884 · 2023-02-16 ·

[Problem] To provide a phononic material that exhibits a voltage-current characteristic to make current flow even when there is no potential gradient, and a method for producing the same. [Solution] A phononic material 1 has a periodic structure body 2′ in which structures 3 are periodically and regularly disposed in a constituent 2, and the periodic structure body 2′ exhibits a voltage-current characteristic to make current flow even when a potential gradient is 0 V. A method for producing the phononic material 1 has such an outline as to carry out a heat treatment to cool and warm the periodic structure body after applying a current with a magnitude to make an electrical resistance characteristic disappear to the periodic structure body 2′ having the electrical resistance characteristic that exhibits an electrical resistance value of 0Ω or less.

Preparation method and device of inductance element, inductance element, and superconducting circuit

A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

PHONONIC MATERIAL AND METHOD FOR PRODUCING SAME
20230044423 · 2023-02-09 ·

[Problem] To provide a phononic material that exhibits an electrical resistance characteristic less than or equal to 0Ω, a precursor of the same, and a method for producing these. [Solution] A phononic material 1 has a periodic structure body 2′ in which structures 3 are periodically and regularly disposed in a constituent 2. The periodic structure body 2′ exhibits an electrical resistance characteristic less than or equal to 0Ω, and has a temperature region that exhibits the electrical resistance characteristic in a temperature range exceeding a superconducting transition temperature when the constituent 2 has the superconducting transition temperature. A method for producing a precursor of the phononic material 1 includes a pretreatment process to obtain the precursor by carrying out a heat treatment to warm the periodic structure body after cooling the periodic structure body in a state of applying a unidirectional current to the periodic structure body 2′.

CRYO-COMPATIBLE QUANTUM COMPUTING ARRANGEMENT AND METHOD FOR PRODUCING A CRYO-COMPATIBLE QUANTUM COMPUTING ARRANGEMENT
20230043673 · 2023-02-09 ·

A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electrically conductive.

SEMICONDUCTOR-FERROMAGNETIC INSULATOR-SUPERCONDUCTOR HYBRID DEVICES

A semiconductor-ferromagnetic insulator-superconductor hybrid device comprises a semiconductor component, a ferromagnetic insulator component, and a superconductor component. The semiconductor component has at least three facets. The ferromagnetic insulator component is arranged on a first facet and a second facet. The superconductor component is arranged on a third facet and extends over the ferromagnetic insulator component on at least the second facet. The device is useful for generating Majorana zero modes, which are useful for quantum computing. Also provided are a method of fabricating the device, and a method of inducing topological behaviour in the device.

METHOD OF FABRICATING A HOLLOW WALL FOR CONTROLLING DIRECTIONAL DEPOSITION OF MATERIAL

A method of fabricating a hollow wall for controlling directional deposition of material comprises: forming a layer of resist on a substrate; removing a portion of the resist selectively to form a channel in the resist; forming a layer of an amorphous dielectric material in the channel; and removing the resist to form the hollow wall. The channel has a front surface configured to prevent bending of a corresponding front face of the hollow wall. The hollow wall is useful for controlling deposition of material when fabricating semiconductor-superconductor hybrid devices, for example. By configuring the channel appropriately, bending of the hollow wall can be prevented, allowing for more precise deposition of material. Also provided is a further method of fabricating a hollow wall; and a method of fabricating a device using the hollow walls.

METHOD OF SELECTIVELY ETCHING A METAL COMPONENT

A method of selectively etching a metal component of a workpiece further comprising a ferromagnetic insulator component. The method comprises contacting the metal component with an etchant solution. The etchant solution comprises a basic etchant and a solvent. The method is useful in the context of the fabrication of semiconductor-superconductor-ferromagnetic insulator hybrid devices, for example. The etchant solution may not attack the ferromagnetic insulator component. Also provided is a composition for etching a metal, and a kit comprising the composition and a composition for depositing a styrene-acrylate co-polymer on a surface.

Superconductor-semiconductor fabrication

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

System and method for superconducting multi-chip module

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

METHODS FOR FABRICATING SUPERCONDUCTING INTEGRATED CIRCUITS
20230240154 · 2023-07-27 ·

Methods of forming superconducting integrated circuits are discussed. The method includes depositing a first superconducting metal layer to overlie at least a portion of a substrate, depositing a dielectric layer to cover a first region of the first superconducting metal layer, pattering the dielectric layer to expose at least a portion of the first region of the first superconducting metal layer and form an opening, and depositing a second superconducting metal layer at an ambient temperature that is less than a melting temperature of the second superconducting metal layer such that the second superconducting metal layer fills the opening and conductively contacts the at least a portion of the first region of the first superconducting metal layer.