An electronic component (10) is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies (16, 18), for initializing the quantum mechanical state of a qubit.

A qubit memory cell having a thin, optically transparent, metal surface gate that laterally fits into the corresponding region of the memory cell, while not being in direct contact with the perimeter of the region. The surface gate may have apertures to accommodate therein the dot-like control electrodes of the qubit and enable the corresponding electrical overpass bridges to be connected to those dot-like control electrodes. The thickness of the surface gate may be selected such as to let a substantial portion of light impinging thereupon penetrate to the underlying surface of the substrate. In at least some embodiments, the electrical-interconnect structure of the memory cell may be designed to enable separate electrical biasing of the surface gate, e.g., independent of the electrical biasing of some other electrodes of the memory cell. Advantageously, such a surface gate may significantly reduce detrimental clumping of charge carriers in the memory cell.

A method of producing a quantum conveyor includes: forming a pair of screening gate electrodes in or on a semiconductor substrate and that extend between a first stationary quantum dot and a second stationary quantum dot, the pair of screening gate electrodes configured to delimit a channel of moveable quantum dots between the first stationary quantum dot and the second stationary quantum dot; forming, via a lithography process, a plurality of first planar transfer electrodes above the semiconductor substrate and that extend transverse to the channel of moveable quantum dots; and forming, via a self-aligned damascene process, a plurality of second planar transfer electrodes laterally interleaved with the first planar transfer electrodes, wherein the first planar transfer electrodes and the second planar transfer electrodes are configured to transfer quantum information between the first stationary quantum dot and the second stationary quantum dot through the channel of moveable quantum dots.

An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively. The first, second, fourth and fifth electric potentials are controllable to define an electrical potential well to confine quantum charge carriers in an elongate quantum dot beneath the elongate channel. The fourth and fifth electric potentials and the position of the fourth and fifth metallic structures define first and second ends of the elongate channel respectively. The width of the electrical potential well is defined by the position of the first and second metallic structures and their corresponding electric potentials; and the length of the electrical potential well is defined by the position of the fourth and fifth metallic structures and their corresponding electric potentials. The third electric potential is controllable to adjust quantum charge carrier energy levels in the electrical potential well.

Systems and methods for controlling one or more qubits in a quantum processor are disclosed. The system comprises a quantum processor comprising one or more spin-based qubits; and a dielectric resonator positioned in proximity to the quantum processor. The dielectric resonator provides a magnetic field. The quantum processor is positioned in a portion of the magnetic field provided by the resonator such that the portion of the magnetic field controls the spin transitions of the one or more spin-based qubits of the quantum processor.

A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions;
wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.

A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

An atomic orbital based memory storage is provided that includes a plurality of surface atoms forming dangling bonds (DBs) and a subset of the plurality of surface atoms passivated with spatial control to form covalent bonds with hydrogen, deuterium, or a combination thereof. The atomic orbital based data storage that can be rewritten and corrected as needed. The resulting data storage is also archival and capable of high data densities than any known storage as the data is retained in a binary storage or a given orbital being passivated or a dangling bond (DB). A method of forming and reading the atomic orbital data storage is also provided. The method including selectively removing covalent bonds to form dangling bonds (DBs) extending from a surface atom by hydrogen lithography and imaging the covalent bonds spatially to read the atomic orbital data storage.

A semiconductor device includes a layer of a semiconductor material in which is formed an active zone; a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in part the active zone; a plurality of second gates forming a plurality of columns; at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, and a first electrode and a second electrode situated on either side of the plurality of measurement gates in the active zone.