The invention relates to a method of manufacturing a device, the device comprising a superconducting zone (20) and an insulating zone (22) in an arrangement, comprising the steps of: depositing a buffer layer (12) on a portion of a substrate (10), etching the buffer layer (12) to obtain two zones (Z1, Z2), each first zone (Z1) being a zone in which the substrate (10) is covered by the buffer layer (12) and intended to form a respective superconducting zone (20), each second zone (Z2) being a zone in which the substrate (10) is exposed to form a respective insulating zone (22), and depositing a second layer (18) of superconducting material on the entire substrate portion (10), the first layer (12) being made of at least two superimposed sub-layers (14, 16).

A method and a device for preparing an inductance element, an inductance element, and a superconducting circuit are provided. The method includes acquiring a compound for preparing an inductance element, a superconducting coherence length and a magnetic field penetration depth of the compound meeting a preset condition; and annealing the compound to cause decomposition between a non-superconductor phase and a superconductor phase in the compound to generate the inductance element, the kinetic inductance of the inductance element being greater than the geometric inductance of the inductance element.

A gated Josephson junction includes a substrate and a vertical Josephson junction formed on the substrate and extending substantially normal the substrate. The vertical Josephson junction includes a first superconducting layer, a semiconducting layer, and a second superconducting layer. The first superconducting layer, the semiconducting layer, and the second superconducting layer form a stack that is substantially perpendicular to the substrate. The gated Josephson junction includes a gate dielectric layer in contact with the first superconducting layer, the semiconducting layer, and the second superconducting layer at opposing side surfaces of the vertical Josephson junction, and a gate electrically conducting layer in contact with the gate dielectric layer. The gate electrically conducting layer is separated from the vertical Josephson junction by the gate dielectric layer. In operation, a voltage applied to the gate electrically conducting layer modulates a current through the semiconducting layer of the vertical Josephson junction.

Techniques for forming quantum circuits, including connections between components of quantum circuits, are presented. A trench can be formed in a dielectric material, by removing a portion of the dielectric material and a portion of conductive material layered on top of the dielectric material, to enable creation of circuit components of a circuit. The trench can define a regular nub or compensated nub to facilitate creating electrical leads connected to the circuit components on a nub. The compensated nub can comprise recessed regions to facilitate depositing material during evaporation to form the leads. For compensated nub implementation, material can be evaporated in two directions, with oxidation performed in between such evaporations, to contact leads and form a Josephson junction. For regular nub implementation, material can be evaporated in four directions, with oxidation performed in between the third and fourth evaporations, to contact leads and form a Josephson junction.

A superconducting junction comprises: a first layer and a second layer of superconducting material; a tunneling layer of insulating material disposed between the first layer and the second layer of the superconducting material; and a layer of thermally conducting, non-superconducting material disposed between the first layer and the second layer of the superconducting material, the non-superconducting layer being in contact with either the first layer or the second layer of superconducting material.

A superconducting junction comprises: a first layer and a second layer of superconducting material; a tunneling layer of insulating material disposed between the first layer and the second layer of the superconducting material; and a layer of thermally conducting, non-superconducting material disposed between the first layer and the second layer of the superconducting material, the non-superconducting layer being in contact with either the first layer or the second layer of superconducting material.

A method of fabricating a superconducting-semiconducting stack includes cleaning a surface of a substrate, the substrate comprising a group IV element; depositing an insulating buffer layer onto the substrate, the insulating buffer layer comprising the group IV element; depositing a p-doped layer onto the insulating buffer layer; depositing a diffusion barrier onto the p-doped layer; and processing the superconducting-semiconducting stack through dopant activation.

An evaporatively cooled device and a system including the same. In some embodiments, the system includes an oligolayer conductive sheet; a superconductor; a tunneling barrier, between the oligolayer conductive sheet and the superconductor; and a bias circuit, configured to apply a bias voltage across the tunneling barrier, the bias voltage being less than a gap voltage of the superconductor and greater than one-half of the gap voltage of the superconductor.

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Josephson junctions (JJ) based on bilayers of azimuthally misaligned two-dimensional materials having superconducting states are provided. Also provided are electronic devices and circuits incorporating the JJs as active components and methods of using the electronic devices and circuits. The JJs are formed from bilayers composed of azimuthally misaligned two-dimensional materials having a first superconducting segment and a second superconducting segment separated by a weak-link region that is integrated into the bilayer.