A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

A memory cell comprises a nanowire structure comprising a channel region and source/drain regions of a transistor. The nanowire structure also comprises as first conductor of a capacitive device as a vertical extension of the nanowire structure.

A memory device includes a selector and a memory cell. The selector includes a first electrode layer, a second electrode layer and a selector layer between the first electrode and the second electrode. The selector layer includes a first element selected from a group consisting of silicon (Si), germanium (Ge), tin (Sn) and aluminum (Al), a second element selected from a group consisting of oxygen (O) and nitrogen (N), and a third element selected from a group consisting of tellurium (Te), selenium (Se) and antimony (Sb).

A semiconductor memory device includes a substrate and a transistor disposed on the substrate. The transistor includes a source doped region, a drain doped region, a channel region, and a gate over the channel region. A data storage region is in proximity to the transistor and recessed into the substrate. The data storage region includes a ridge and a V-shaped groove. A bottom electrode layer conformally covers the ridge and V-shaped groove within the data storage region. A resistive-switching layer conformally covers the bottom electrode layer. A top electrode layer covers the resistive-switching layer.

In fabrication of a phase change random access memory (PCRAM), a field effect transistor (FET) logic layer is formed on a first wafer, including a heating FET for each storage cell. The FET logic layer is transferred from the first wafer to a carrier wafer. Thereafter, a storage layer of the PCRAM is formed on the exposed surface of the FET logic layer, including a region of a phase change material for each storage cell that is electrically connected to a channel of the heating FET of the storage cell. The storage layer further includes a second heating transistor for each storage cell that is electrically connected to a channel of the second heating transistor.