Metal oxide based memory devices and methods for manufacturing are described herein. A method for manufacturing a memory cell includes forming a bottom adhesion layer in a via formed in an insulating layer. Forming a bottom conductive plug in the bottom adhesion layer. Forming a top adhesion layer over the bottom adhesion layer and bottom conductive plug. Forming a top conductive plug in the top adhesion layer. Wherein the thickness of the bottom and top adhesion layers may be different from one another.

There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.

An approach to provide a semiconductor structure for a resistive switch device. The resistive switch device includes a bottom electrode, a dielectric material over the bottom electrode, and a metal oxide material on a portion of the dielectric material connecting to a portion of a top electrode where the metal oxide material has a controlled volume. Additionally, the approach includes a plurality of the resistive switch devices in a crossbar. The crossbar array includes the plurality of resistive switch devices on more than one bottom electrode and at least one top electrode connecting to the plurality of resistive switch devices.

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.

A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.

The present disclosure provides a self-rectifying resistive memory, including: a lower electrode; a resistive material layer formed on the lower electrode and used as a storage medium; a barrier layer formed on the resistive material layer and using a semiconductor material or an insulating material; and an upper electrode formed on the barrier layer to achieve Schottky contact with the material of the barrier layer; wherein, the Schottky contact between the upper electrode and the material of the barrier layer is used to realize self-rectification of the self-rectifying resistive memory. Thus, no additional gate transistor or diode is required as the gate unit. In addition, because the device has self-rectifying characteristics, it is capable of suppressing read crosstalk in the cross-array.

Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

A resistance switching memory device is provided, including an insulating layer having a top surface, a bottom electrode embedded in the insulating layer, a resistance switching layer disposed on the bottom electrode, and a top electrode formed on the resistance switching layer and covering the resistance switching layer. Also, the bottom electrode has an upper portion protruding from the top surface of the insulating layer, and the upper portion has round corners at edges.

A nanoporous (NP) memory may include a non-porous layer and a nanoporous layer sandwiched between the bottom and top electrodes. The memory may be free of diodes, selectors, and/or transistors that may be necessary in other memories to mitigate crosstalk. The nanoporous material of the nanoporous layer may be a metal oxide, metal chalcogenide, or a combination thereof. Further, the memory may lack any additional components. Further, the memory may be free from requiring an electroformation process to allow switching between ON/OFF states.