Disclosed in Disclosed are a resistive random access memory and a manufacturing method. A memory area of the resistive random access memory comprises a first metal interconnection line, a resistive random access memory unit and a second metal interconnection line that are connected in sequence, wherein the whole or part of a bottom electrode of the resistive random access memory unit is arranged in a short through hole of a barrier layer on the first metal interconnection line; the first metal interconnection line is connected to the bottom electrode of the resistive random access memory unit; and the second metal interconnection line is connected to a top electrode of the resistive random access memory unit. By means of arranging the whole or part of the bottom electrode of the resistive random access memory unit in the short through hole of the barrier layer on the first metal interconnection line, the bottom electrode can be made to be very thin, such that the height of the resistive random access memory unit in a CMOS back end of line is reduced, the thickness, which needs to be occupied, of each layer in the CMOS back end of line is smaller, integration is facilitated, the back end of line of a logic circuit area cannot be influenced, and the total stacking thickness can meet the electrical property requirement of the resistive random access memory. The process integration scheme in the embodiments of the present application can make the integration of an RRAM and a standard CMOS simpler.

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Memristors, including memristors comprising a Schottky barrier, and related systems and methods are generally described.

A method of manufacturing an electronic device comprises: forming a plurality of line patterns on a substrate extending in a first direction and including a first conductive line and a memory pattern; forming a first liner layer on sidewalls of each of the plurality of line patterns, the first liner layer including a plurality of layers having different energy band gaps; forming an insulating interlayer on the substrate; forming a plurality of second conductive lines on the line patterns and the insulating interlayer; etching the first liner layer, the insulating interlayer and the memory pattern using the second conductive lines as an etch barrier to expose the first conductive line to form a plurality of memory cells; and forming a second liner layer on both sidewalls of each of the memory cells, the etched first liner layer and both sidewalls of the etched insulating interlayer.

A semiconductor memory device includes a substrate, a dielectric layer on the substrate, and a contact plug in the dielectric layer. An upper portion of the contact plug protrudes from a top surface of the dielectric layer. The upper portion of the contact plug acts as a first electrode. A buffer layer is disposed on the dielectric layer and beside the upper portion of the contact plug. A resistive-switching layer is disposed beside the buffer layer. A second electrode is disposed beside the resistive-switching layer.

Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a filament and one or more lateral regions including a doping material that are between a top region and a bottom region of the switching layer. The RRAM further includes a top electrode disposed above the switching layer.

A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H.sub.2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.

Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

Embodiments of process flows and methods are provided for forming a resistive switching random access memory (ReRAM). More specifically, process flows and methods are provided for reducing the forming voltage needed to form a conductive path in the ReRAM cells. A wide variety of plasma doping processes are used to introduce a plurality of different dopants into a metal-oxide dielectric film. By utilizing at least two different dopants, the plasma doping processes described herein reduce the forming voltage of the subsequently formed ReRAM cell compared to conventional processes that use only one dopant. In some embodiments, the forming voltage may be further reduced by applying a bias power during the plasma doping process, wherein the bias power is preselected to increase the number of ions introduced into the metal-oxide dielectric film during the plasma doping process.

Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, processes are described in which a correlated electron material film may be formed over a conductive substrate by converting at least a portion of the conductive substrate to CEM.