Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

A non-volatile memory structure, and methods of manufacture, which may include a first memory element and a second memory element between a first terminal and a second terminal. The first memory element and the second memory element may be in parallel with each other between the first and second terminal. This may enable the hybrid non-volatile memory structure to store values as a combination of the conductance for each memory element, thereby enabling better tuning of set and reset conductance parameters.

A resistive random access memory (RRAM) device includes a plurality of memory cells, each of at least a subset of the memory cells including first and second electrodes and an organic thin film compound mixed with silver perchlorate (AgClO.sub.4) salt as a base layer that is incorporated with a prescribed quantity of inorganic metal oxide molecules using vapor-phase infiltration (VPI), the base layer being formed on an upper surface of the first electrode and the second electrode being formed on an upper surface of the base layer. Resistive switching characteristics of the RRAM device are controlled as a function of a concentration of AgClO.sub.4 salt in the base layer. A variation of device switching parameters is controlled as a function of an amount of infiltrated metal oxide molecules in the base layer.

A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.

Disclosed is a resistive switching element. The resistive switching element includes a first oxide layer and a second oxide layer stacked one on top of the other such that an interface is present therebetween, wherein the first oxide layer and the second oxide layer are made of different metal oxides; two-dimensional electron gas (2DEG) present in the interface between the first oxide layer and the second oxide layer and functioning as an inactive electrode; and an active electrode disposed on the second oxide layer, wherein when a positive bias is applied to the active electrode, an electric field is generated between the active electrode and the two-dimensional electron gas, such that the second oxide layer is subjected to the electric field, and active metal ions from the active electrode are injected into the second oxide layer. The resistive switching element realizes highly uniform resistive switching operation.

A RRAM device is provided. The RRAM device includes: a bottom electrode in a first dielectric layer; a switching layer in a second dielectric layer over the first dielectric layer, wherein a conductive path is formed in the switching layer when a forming voltage is applied; and a tapered top electrode region in a third dielectric layer over the second dielectric layer, wherein the tapered top electrode region extends downwardly into the switching layer.

An OxRAM resistive memory cell includes a lower electrode, an upper electrode, and an active layer which extends between the lower electrode and the upper electrode. The active layer includes a layer of a first electrically insulating oxide, wherein an electrically conductive filament can be formed, then subsequently broken and reformed several times successively. The upper electrode includes a reservoir layer, capable of receiving oxygen, which includes an upper part made of a metal and a lower part made of a second oxide, the second oxide being an oxide of the metal and including a proportion of oxygen such that the second oxide is electrically conductive.

Some embodiments relate to a memory device. The memory device includes a bottom electrode overlying a substrate. A data storage layer overlies the bottom electrode. A top electrode overlies the data storage layer. A conductive bridge is selectively formable within the data storage layer to couple the bottom electrode to the top electrode. A diffusion barrier layer is disposed between the data storage layer and the top electrode.

A memory device is disclosed. The memory device includes a bottom contact, and a memory layer connected to the bottom contact, where the memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode, and a first barrier layer, including a first oxide material and a second oxide material, where the first oxide material is different from the second oxide material, and where the first barrier layer is between one of A) the memory layer and the bottom contact, and B) the top electrode and the top contact, where the first barrier layer is configured to substantially prevent the conduction of ions or vacancies therethrough.

Some embodiments relate to a method for forming an integrated chip. The method includes forming a bottom electrode over a substrate. A data storage layer is formed on the bottom electrode. A diffusion barrier layer is formed over the data storage layer. The diffusion barrier layer has a first diffusion activation temperature. A top electrode is formed over the diffusion barrier layer. The top electrode has a second diffusion activation temperature less than the first diffusion activation temperature.