A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

A memory array, a semiconductor chip and a method for forming the memory array are provided. The memory array includes first signal lines, second signal lines and memory cells. The first signal lines extend along a first direction. The second signal lines extend along a second direction over the first signal lines. The memory cells are defined at intersections of the first and second signal lines, and respectively include a resistance variable layer, a switching layer, an electrode layer and a carbon containing dielectric layer. The switching layer is overlapped with the resistance variable layer. The electrode layer lies between the resistance variable layer and the switching layer. The carbon containing layer laterally surrounds a stacking structure including the resistance variable layer, the switching layer and the electrode layer.

A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

The present disclosure includes apparatuses and methods related to forming memory cells having memory element dimensions. For example, a memory cell may include a first electrode, a select-element material between the first electrode and a second electrode, and a lamina between the select-element material and the first electrode. The first electrode may comprise a first portion, proximate to the lamina, having a first lateral dimension; and a second portion, distal from the lamina, having a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension.

A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

A memory cell formed in a pillar structure between a first electrode and a second electrode includes laminated encapsulation structure. In one example, the pillar includes a body of ovonic threshold switch material, carbon-based intermediate layers, metal layers and a body of phase change memory material in electrical series between the first and second electrodes. The laminated encapsulation structure surrounds the pillar. The laminated dielectric encapsulation structure comprises at least three conformal layers, including a first layer of material, a second conformal layer of a second layer material different from the first layer material; and a third conformal layer of a third layer material different from the second layer material.

A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.

A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.

A memory device includes a first interconnect layer, a second interconnect layer, a phase-change layer, and an adjacent layer. The phase-change layer is disposed between the first interconnect layer and the second interconnect layer and configured to reversibly transition between a crystalline state and an amorphous state. The adjacent layer contacts the phase-change layer and comprises tellurium and at least one of titanium, zirconium, or hafnium.