Y10S358/9091

Handheld imaging device incorporating multi-core image processor
09584681 · 2017-02-28 · ·

A handheld imaging device includes an image sensor for sensing an image; a processor for processing the sensed image; a plurality of processing units provided in the processor, the plurality of processing units connected in parallel by a crossbar switch to form a multi-core processing unit for the processor; and an image sensor interface for converting signals from the image sensor to a format readable by the plurality of processing units, the image sensor interface sharing a wafer substrate with the processor. A transfer of data from the image sensor interface to the plurality of processing units is conducted entirely on the shared wafer substrate.

Handheld imaging device with VLIW image processor
09560221 · 2017-01-31 · ·

A handheld imaging device includes an image sensor for sensing an image: a Very Long Instruction Word (VLIW) processor for processing the sensed image; a plurality of processing units provided in the VLIW processor, the plurality of processing units connected in parallel by a crossbar switch to form a multi-core processing unit for the VLIW processor; and an image sensor interface for receiving signals from the image sensor and converting the signals to a format readable by the VLIW processor, the image sensor interface sharing a wafer substrate with the VLIW processor. A transfer of data from the image sensor interface to the VLIW processor is conducted entirely on the shared wafer substrate.

Multi-core image processor for portable device
09544451 · 2017-01-10 · ·

A portable handheld device including a CPU for processing a script; a multi-core processor for processing an image; an input buffer for receiving data for processing by the multi-core processor, the input buffer being provided under the control of the multi-core processor to send data thereto; and an output buffer for receiving data processed by the multi-core processor, the output buffer being provided under the control of the multi-core processor to receive data therefrom. The multi-core processor comprises a plurality of micro-coded processing units. The CPU is configured with authority to clear and query the input and output buffers.