Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface, and wherein a second bump placement restriction specifies an allowed distance range between the bump and a qubit chip element in a layout of a second surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal between the first surface and the second surface and is positioned according to the set of bump placement restrictions.

Vacuum deposited thin films of material are used to create an interface that non-preferentially interacts with different domains of an underlying block copolymer film. The non-preferential interface prevents formation of a wetting layer and influences the orientation of domains in the block copolymer. The purpose of the deposited polymer is to produce nano structured features in a block copolymer film that can serve as lithographic patterns.