Method and apparatus for reduction of solar cell LID

Abstract

Reduction of solar wafer LID by exposure to continuous or intermittent High-Intensity full-spectrum Light Radiation, HILR, by an Enhanced Light Source, ELS, producing 3-10 Sols, optionally in the presence of forming gas or/and heating to within the range of from 100° C.-300° C. HILR is provided by ELS modules for stand-alone bulk/continuous processing, or integrated in wafer processing lines in a High-Intensity Light Zone, HILZ, downstream of a wafer firing furnace. A finger drive wafer transport provides continuous shadowless processing speeds of 200-400 inches/minute in the integrated furnace/HILZ. Wafer dwell time in the peak-firing zone is 1-2 seconds. Wafers are immediately cooled from peak firing temperature of 850° C.-1050° C. in a quench zone ahead of the HILZ-ELS modules. Dwell in the HILZ is from about 10 sec to 5 minutes, preferably 10-180 seconds. Intermittent HILR exposure is produced by electronic control, a mask, rotating slotted plate or moving belt.

Claims

1. Method of treating Si wafers for solar cells to reduce Light Induced Degradation (LID) resulting from in-use operation of said solar cells during exposure to sunlight, comprising the steps of: a. orienting a plurality of Si wafers having top and bottom planar surfaces with said top surfaces facing upwardly; b. transporting said plurality of Si wafers continuously and sequentially in a linear direction through a treatment zone in a generally horizontal processing path; c. exposing said top surfaces of said Si wafers with full-spectrum light radiation from Light Emitting Plasma (LEP) lamps, in an amount of 3 Sols to 10 Sols for a time period of from 10 seconds to 5 minutes sufficient to reduce LID that would otherwise be exhibited by said wafers; and d. heating said wafers during exposure to said full-spectrum light radiation by use of Infrared Radiation (IR) lamps directed onto said top surfaces of said Si wafers, said IR wafer heating lamps being controlled separately from said Light Emitting Plasma (LEP) lamps, to maintain a temperature of said wafers in a range of 100° C.-300° C.

2. Method as in claim 1 wherein said step of exposure of of said top surfaces of said wafers to said full-spectrum light radiation is controlled so that said exposure is intermittent, alternating between said full-spectrum light radiation impinging on said wafers surfaces, ON, and said full-spectrum light radiation not impinging on said wafers surfaces, OFF.

3. Method as in claim 2 wherein said IR wafer heating lamps are maintained ON during said step of intermittent exposure of said wafers to said full spectrum light from said LEP lamps to maintain said wafer temperature within said range of 100° C.-300° C.

4. Method as in claim 1 which includes a step of firing said wafers prior to said full-spectrum light radiation treatment so that said wafers firing and said full-spectrum light radiation treatment of said wafers comprise a sequentially continuous process.

5. Method as in claim 1 wherein said LEP and IR lamps are disposed in an alternating array above the top surface of said wafers.

6. Method as in claim 5 wherein said LEP lamps are separated from said wafer transport path by a window selected from a group comprising of quartz, Vvcor and high temperature transparent glass.

7. Method as in claim 6 which includes a step of providing a forming gas consisting essentially of H.sub.2 in said treatment zone.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention is described in more detail with reference to the drawings, in which:

(2) FIG. 1 is a schematic of a full wafer processing line showing by way of example, alternate LEP module locations A and B, as well as alternate Boron application locations and modules;

(3) FIG. 2 is an isometric view of a furnace showing a high-intensity HILZ radiation module of the Example I type disposed downstream of the firing/quench zones;

(4) FIG. 3 is a vertical section view along line 2-2 of FIG. 2 showing the Example I-type ELS module and shroud above the wafer line, in this example a finger drive transport system being illustrated;

(5) FIG. 4 is a vertical view, partly in section of the Example I-type ELS module of FIGS. 1 and 2 showing the light source and the reflector, as well as the housing in relation to a wafer being transported by a finger drive transport system;

(6) FIG. 5 is a side elevation of a metallization furnace employing a plurality of Example II-type ELS modules (LEP lamps), in series, downstream of the furnace quench zone, in this example the LEP modules being integrated in the line upstream of an annealing zone;

(7) FIG. 6A is an isometric of the Example II ELS module showing a housing containing four LEP light sources;

(8) FIG. 6B is a partial vertical section view along line 6B-6B of FIG. 6A showing one example of a cooling air flow path, the wafer transport being shown below the LEP lamps and the wafers heated by a platen heater;

(9) FIGS. 7A-7D are a related series of views showing use of a shadow mask to produce intermittent, strobing, high-intensity full-spectrum light treatment of wafers, in which:

(10) FIG. 7A is a side elevation view of a pair of ELS lamp modules of the HILZ-B zone upstream of an annealing zone as in FIG. 5 showing the use of a light mask and the relation to the wafers being transported in one or two lines;

(11) FIG. 7B is a section view, taken along the longitudinal center of an ELS of FIG. 7A, showing the location of the shadow mask with reference to the ELS bulb and the wafer transport;

(12) FIG. 7C is a plan view of an ELS shadow mask for producing the reduced-intensity shadow lines for intermittent ON-OFF illumination exposure (strobing) to wafers as they pass under the ELS lamps during processing in the HILZ; and

(13) FIG. 7D is an enlargement of a section of the shadow mask of FIGS. 7B and 7C showing the proportions of mask thickness, gap to the top surface of the wafer and the Light ON and OFF intervals.

DETAILED DESCRIPTION OF THE INVENTION

(14) The following detailed description illustrates the invention by way of example, not by way of limitation of the scope, equivalents or principles of the invention. This description will clearly enable one skilled in the art to make and use the invention, and describes several embodiments, adaptations, variations, alternatives and uses of the invention.

(15) In this regard, the invention is illustrated in the several figures, and is of sufficient complexity that the many parts, interrelationships, and sub-combinations thereof simply cannot be fully illustrated in a single patent-type drawing. For clarity and conciseness, several of the drawings show in schematic, or omit, parts that are not essential in that drawing to a description of a particular feature, aspect or principle of the invention being disclosed. Thus, details of one embodiment of one feature may be shown in one drawing, and the details of another feature will be called out in another drawing.

(16) FIG. 1 shows a schematic of an exemplary solar cell wafer integrated processing line apparatus 10 in accord with the invention, in which prepared wafers 12 are continuously transported during processing from the input end, I, to the output end 0 in the direction of the arrows via a conveyor transport system 13, in this embodiment via a finger transport system as disclosed in detail in our U.S. Pat. No. 8,829,396. UV module 14 provides a zone for UV pre-treatment to one or both the top or/and bottom surface of the wafers 12. Doper 16 applies a P-containing compound or solution (e.g., concentrated phosphoric acid) to the upper surface of the wafers 12. Optionally, the wafers can be flipped-over (not shown) and the bottom surface coated with a B-containing compound or solution (e.g., boric acid) at this stage 16. The surface-coated wafers are dried with high-intensity IR Lamp(s) and fed into and through an IR-Lamp heated diffusion furnace 18 for diffusion firing of the P or co-firing of the P and B into the wafer silicon to dope it. The high-intensity IR Lamps in the diffusion furnace 18 are designated IR.sub.L in FIG. 1. Exemplary UV pre-treaters, dopers, driers and firing furnace apparatus and operational methods are disclosed in our U.S. Pat. No. 8,742,532. Introduction of P and/or B is shown schematically in FIG. 1 via sprayers identified “P/B” for zone 16 and “B/P” for zone 22, respectively.

(17) Following the diffusion firing zone 18 is an ARC coating apparatus 20, which coats an anti-reflective coating onto the P-doped upper surface of the wafers. Optionally, following ARC coating in zone 20, the wafers can be flipped-over and the bottom side doped with a B-compound in zone 22 and dried. In that case, the wafers are then flipped again for introduction into ELS-containing HILZ apparatus 24A (ELS/HILZ Zone A) wherein the top or/and bottom surface(s) are exposed to high-intensity full visible spectrum radiation, HILR, by ELS lamps (disclosed above, and in more detail below). The number of ELS lamps in zone 24A will be selected for the desired exposure dwell time at the selected, controlled transport conveyor rate of the furnace, and the light intensity within the range of from about 3 Sols to about 10 Sols. Exemplary lamps are LEP, Xenon, Halogen or LED type lamps to provide the high-intensity full-spectrum light radiation, HILR. The HILR exposure treatment in ELS/HILZ zone 24A may also be accompanied by exposure to a forming gas having from 2-90% H.sub.2 and the balance N.sub.2. The wafers may be heated to within the range of from about 100° C. to about 300° C., e.g., by a platen heater or resistance coils, 50, disposed beneath the wafers and located in the gap between the transport fingers. Optionally, the wafers may be heated from below or/and from above by use of suitably located high-intensity IR lamps of the type used in the diffusion or metallization furnaces of this line.

(18) The irradiated wafers exit ELS/HILZ Zone A, 24A, into printer 26 which applies a fine grid of Ag-based paste to the top (P-doped) surface of the wafers and a full surface area, Al-based paste to the bottom (B-doped) surface of the wafers, and dried. The doped, diffusion-fired, ARC-coated and printed wafers (and optionally irradiated) are then fed into a multi-zone, high-intensity, IR-Lamp heated metallization furnace 28, which includes a burn-out and pre-heat zones 28a, a peak firing zone 28b, and a quench zone 28c containing air knives to quickly cool the wafers from peak firing of in the range of from about 800° to about 1050° C. The high-intensity IR lamps in the metallization furnace 28 are designated IR.sub.L in FIG. 1.

(19) In this example a metallization furnace having one or more isolation lamp module(s) forming the peak firing zone 28b includes a quartz window separating the wafer processing zone through which the transport drive moves the wafers from the high-intensity IR lamp zone. This isolation configuration permits supply of the forming gas to the wafers in the peak firing zone, and in the adjacent downstream ELS/HILZ Zone B, 30. In FIG. 1, the forming gas is shown as introduced via lines F.sub.I. In addition, the quench zone 28C of the firing (metallization) furnace 28 employs “air” knives with compressed gas streams directed to the top and bottom of the wafers to instantaneously cool them from the peak firing temperature down to the processing temperature of the ELS/HILZ Zone B. The “air” knives can employ compressed forming gas to maintain continuity of the atmosphere of H2/N2 from the peak firing zone, through the quench zone and into the ELS/HILZ Zone B. In addition the next downstream zone, Annealing Zone 32 optionally may also be maintained under H2 with the forming gas introduced into the firing zone 28b, and the quench zone 28c, flowing with the wafers through the ELS/HILZ Zone B, 30 and thence into the Annealing Zone 32, from which it is ultimately exhausted and burned off. In addition, either or both the ELS/HILZ Zone 30 and the Annealing Zone 32 may include platen heaters or open coil resistance element below the wafers, indicated as PLH in FIG. 1. Excess forming gas is withdrawn from the Annealing Zone 32 via exhaust F.sub.O, and may optionally be removed at the curtain walls defining the downstream end of zones 28b, 28c and 30, as needed (not shown). In the ELS/HILZ Zone B, 30, the ELS lamps may be disposed above, and optionally also below, the wafers, indicated, respectively as upper lamps 30U and lower lamps 30L.

(20) FIG. 2 shows in isometric projection, the Metallization firing furnace 28, followed by the ELS-containing HILZ Zone B, 30, and the Annealing Zone 32. The metallization furnace is disposed upstream of, and connected to the HILR treatment zone, HILZ-B. The finger drive wafer transport system 13 can be seen in the right hand section of the ELS/HILZ Zone 30 and Annealing Zone 32, in which the ELS modules and housing for the top of the annealing zone have been removed to show detail. The conveyor system of the metallization furnace is extended into and functions as the HILR treatment zone, HILZ-B so that the transport of the wafers is continuous through the integrated processing apparatus.

(21) The left end of FIG. 2 shows the initial burn-out zone BOZ of the pre-heat section 28a, with the manifold and volatiles exhaust pipe assembly 34 collecting the paste volatiles burnt out of the printed wafer coatings being removed at that point. The ports in the sides of the furnace sections are labeled IR.sub.L as in FIG. 1. As shown there is a greater concentration of the high-intensity IR lamps in the peak firing zone 28b. The quench zone 28c includes an exhaust plenum and stack 36 as needed. Shown for the ELS in this embodiment is an upper LEP-type Lamp module 30U, connected to its power supply 38 (which may be separately cooled, not shown). Coolant fluid, such as air and/or water, to cool ELS/LEP Lamp 30 U is introduced or/and withdrawn via lines 40. The Annealing zone 32 comprises a forced air cooling housing to anneal the wafers and reduce the temperature of the wafers so they can be handled at the output end of the line (see FIG. 1).

(22) Continuing with the embodiment in which LEP-type ELS lamps are used in the HILR treatment zone, HILZ-B, FIG. 3 shows in transverse section view along line 3-3 of FIG. 2, the ELS/LEP Lamp module 30U, disposed in association with the finger drive transport conveyor 13 carrying wafers 12 through the various zones of the furnace 28. In this example, the furnace 28 is a top lift design in which the upper half 28U, defined along Lift Line LL, is lifted above the fixed lower half 28L. This permits access to the lower half of the furnace for servicing. When there are no wafers being carried by the finger drive 13, access can be had into the lower half of the furnace as well for servicing. The ELS/LEP module of HILZ-B, 30U, comprises a lamp emitter head assembly 42 connected to the power supply 38 (see FIG. 2) and mounted on a bell housing 44 within which is a parabolic reflector (not shown in this figure). In turn the bell housing 44 is mounted on side walls 46 which define a light concentrating shroud. The bottom of the ELS/LEP module is sealed with a quartz, Vycor, or other high temperature transparent glass window 48 so that the wafer process zone, WPZ, is sealed off and self-contained to permit introduction of forming gas in the WPZ to assist in passivating BOC under the high-intensity light radiation of the HILZ lamps. The downstream annealing zone exhaust shroud 32 is seen behind the ELS/LEP module 30U. A resistance heater or hot water heated platen 50 may be disposed below the wafer.

(23) FIG. 4 shows a schematic internal cross section of an ELS/LEP, Example I module 30U or 30L. The lamp head 42 includes the RF plasma emitter 52. The emitter head assembly 42 is mounted on a parabolic reflector 54 having an internal surface 56 coated or formed of high reflectance material. The reflector is mounted on the side-wall housing 46, which is generally square in plan view and the inside walls of which may also be coated with, or formed of, a high reflectance material. The bottom is preferably sealed with a quartz window 48 in the process embodiment employing a forming gas. The ELS/LEP module is shown suspended disposed above the finger drive transport system 13, carrying the wafers 12 through the concentrated, collimated spot of high-intensity light developed by the emitter. The wafers are heated from below in this example by a platen heater 50, or optionally an open coil resistance heater, to within the temperature range of from about 100° C. to about 300° C.

(24) FIG. 5 is a side view of a second embodiment of the inventive furnace in which the ELS/LEP Lamp assembly 10 employs the Example II lamps. The furnace section 28 is as described above. The HILR ELS/LEP Lamp section, HILZ-B, includes, in this example, 4, multi-bulb high-intensity, air and/or water cooled lamp assemblies 60a, 60b, 60c and 60d, arrayed in series, just upstream of a forced air annealing section 32. In this example, forming-gas exhaust manifolds 36 include H.sub.2 oxidizer (igniter) assemblies 58 mounted atop the flue pipes to burn off excess forming gas at the ends of the HILZ-A or HILZ-B.

(25) FIGS. 6A and 6B show the details of the Example II ELS/LEP lamp modules 60a-d. FIG. 6A shows module 60a in isometric projection, comprising upper housing 62 on which are mounted an array of four cooling air input fans 64a, 64b, 64c, and 64d disposed around a central exhaust duct 68. The upper housing is connected to a lower housing 66. Cooling water lines may be used to cool the plasma drivers in the upper housing 62. FIG. 6B shows in vertical section view taken along the line 6B-6B of FIG. 6A, the location of the ELS/LEP lamp module 60a disposed above the wafer finger drive transport system 13 carrying the wafers 12, below which is disposed an optional platen heater 50. The plasma drivers 70a and 70b are shown disposed in the upper housing (the electrical supply and cooling water lines are not shown for clarity). As shown by the arrows representing air flow, cool air is injected in the top of the upper housing by the fans 64b and 64c. The air circulates around the drivers, and then down into the lower housing 66 which contains the plasma bulbs 72a, 72b from which the high-intensity full-spectrum light is generated and directed down onto the wafer 12, just below. Collimators 74 may be used to direct the generated light down onto the wafers. The optional quartz window 48 at the bottom of the lower housing assists in containing the flow of air, and directing it to the central flue 68, where it is exhausted as hot air. The Wafer Processing Zone, WPZ is defined below the window in the path of transport of the wafers as shown. It should be understood that while a single finger drive system 13 is shown carrying a wide wafer 12 in a single processing lane defined by the plane of the wafer transport, dual-lane, side-by-side wafer transport Lines A and B may be used, with the wafers in each respective Line A and Line B centered under the ELS/LEP bulbs 72a and 72b, respectively.

(26) FIGS. 7A-D show embodiments of ELS lamp module(s) 30 disposed in the HILZ-B LID treatment zone (see FIG. 5 for location) employing the Example II, lamps, LEP-type high-intensity full-spectrum lamp bulb 72 within a cylindrical wire mesh or perforated metal radiation shield 86. The ELS lamp modules 30 are arrayed longitudinally in series as shown in FIG. 5, to provide the selected HILZ dwell time for treatment. In FIGS. 7A-7D the wafer transport path is left to right as indicated by Arrow T.

(27) Alternately, FIG. 7A may be viewed as a lateral section view, in which case the transport conveyor(s) are moving toward the viewer and this perspective shows the embodiment of two, side-by-side processing lanes of a dual-lane furnace. In either viewing aspect, the ELS lamp modules 30a, 30b are abutting, but may be spaced apart either longitudinally for a shadow zone, or in the case of a dual-lane furnace, they are spaced apart to provide clearance for the transport mechanism of the lanes. The LEP bulb 72 is located at the focal point of a parabolic reflector 54 which collimates the high-intensity full-spectrum light radiation downwardly onto the wafer 12 being transported by conveyor 13 in direction T. The collimated downwardly directed light is shown schematically by arrows 76. As an alternative to using a parabolic reflector, a collimating Fresnel lens may be used, spaced just below the bulb in the LEP lamp housing 30. When using a Fresnel lens, the parabolic reflector is not required. As before, the fans 64a, 64b cool the respective LEP lamp modules.

(28) In the embodiment calling for intermittent light exposure treatment of the wafers, FIGS. 7A-7D show use of a shadow mask 78 to produce intermittent ON-OFF illumination (strobing) as the wafers pass under the ELS lamp modules 30 in the HILZ-A or HILZ-B. FIGS. 7C and 7D show details of one embodiment of a shadow mask, in this example a metal plate such as aluminum having precise slots 84 cut therein to produce alternating lands 82 between the slots 84. In FIG. 7B the location of the mask as fixed in place to span the aperture of the reflector 54 is shown, with the travelling wafer 12 disposed closely beneath the bottom surface of the mask. In FIG. 7C the wafer 12 is just visible through the slots of the mask 78. To reduce unwanted reflections and penumbra, the slotted Al mask 78 is anodized black.

(29) The mask slots also assist in collimating the light, so that as the wafer passes underneath it, see FIG. 7D, the wafer is alternately exposed to the full-spectrum high-intensity light radiation, followed by a dark interval, then light, and so on. FIG. 7D also shows exemplary proportions of the mask 78 with respect to the distance to the top surface 90 of the wafer 12 as it passes underneath on conveyor 13. In the FIG. 7D example, where the slotted mask plate 78 has a thickness 2x, the gap between the bottom of the mask 88 and the top surface 90 of the wafer is half that, i.e., the distance is x. In this example the widths of the mask lands 82 and the slots 84 are the same, so the “Light ON” interval 92 is equal to the “Light OFF” interval 94. These On/OFF intervals may be lengthened or shortened simply by use of a different mask having a different alternating pattern of widths of lands and slots. In the alternative, increasing or decreasing the rate of travel of the conveyor 13 can control the strobing rate (intervals). Where a forming gas is used in the HILZ, when a slotted metal mask is used, a glass plate is placed below the mask in contact with its surface 88, or placed on the top surface 96 of the mask

(30) As an option to using a shadow mask, a horizontal, rotating thin plate having one or more slots therein at the output aperture of the ELS lamp module may be used. In another alternative, the ELS lamp modules may be spaced apart with suitable vertical shielding extending downwardly to close to the wafer top surface 90 so that the wafers traverse a dark zone between the longitudinally spaced-apart lamps. As an alternative to the use of a slotted metal shadow mask 78, the shadow mask may be a glass plate having dark lines formed on its surface, e.g., by vapor deposition or sputtering thereon a metal layer or opaque oxide layer. The glass may be Vycor, quartz or a high-temperature borosilicate glass. In this alternative embodiment, the shadow mask plate can thus double as the isolation window, permitting use of a forming gas in the wafer-travel processing space, WPZ (see FIG. 6B). In still another embodiment, the shadow mask may be a moving mask rather than fixed in place, such as by use of a slotted, solid belt that is disposed to move in a horizontal path, parallel to the path of the wafers through the HILR treatment zone, HILZ-A or HILZ-B, and located between the output of the ELS module and the wafers to cast alternating bands of HILR and shadow on the wafers passing therebelow. Control of the speeds of the wafer conveyor and the belt mask permits a wide range of intermittent exposure, ON/OFF, strobing intervals. The slotted belt may be moving in the same direction as the wafer transport through the HILR treatment zone, or countercurrent to it (opposite direction), as desired. Belt turners, e.g., angularly-disposed rollers, may be used to divert the belt out of the way of the ELS modules on the return path.

(31) In the preferred shadow mask embodiment, the width and number of the mask shadowing lines are selected with respect to the light output aperture of the ELS module (e.g., 210 mm width) for a standard 6″ wafer being transported along the processing line and the conveyor transport speed (by way of example, 230 inches/minute), to provide rapid strobing (ON) effect on the top surface of the wafer on the order of less than 1 second light radiation exposure between shadow (OFF) modes. The ON/OFF intervals may be equal or unequal as noted above.

(32) Process Examples with Unexpected Results

(33) By way of example of the HILR processing method of this invention, mono-Si solar cell wafers treated with full-spectrum HILR employing an ELS of the apparatus disclosed herein were tested for LID reduction in two series of tests: Test I Series, at 5 Sols intensity with heating at between 150° C.-230° C. for a continuous illumination period in the range of 60-180 seconds; and Test II Series, at >5 Sols intensity with heating at between 230° C.-300° C. for a continuous illumination period in the range of 10-60 seconds. Both Test Series subjected the treated wafers to sunlight exposure (one week) to simulate in-use service to demonstrate LID; both Test Series exhibited unexpectedly improved LID reduction, as follows:

(34) TABLE-US-00001 TABLE 1 Test Series I Test I HILR Solar Conversion SCE, After Test Light Induced Reduction of Wafer Exposure Efficiency (SCE) Exposure, In-Use Degradation, LID, LID, % Com- # In ELS? As Produced, % Simulation, % % Reduction in SCE pared to A A No (Ref.) 20.56 20.51 0.244 N.A. B Yes 20.66 20.65 0.048  19.7 C Yes 20.20 20.22 +0.09 (SCE Increase) 136.9
Test I series results show that longer ELS high-intensity full-spectrum exposure of the wafer top surface produces greater LID reduction, with doubling of time cutting the LID effect (reduction in SCE) by half or more. In addition, that doubling of exposure time effect holds true at all temperatures in the range, but the greater reduction of LID occurs at hotter temperatures in the range.

(35) TABLE-US-00002 TABLE 2 Test Series II Test II HILR Light Induced Reduction of Wafer Exposure Degradation, LID, LID, % Com- # In ELS? % Reduction in SCE pared to A A Reference 0.06 (Normal) N.A. B, D Yes 0.03 50.  C Yes 0.04 33.3
Test Series II shows that at higher temperature and higher intensity of the HILR, the treatment time can be reduced to under 1 minute with unexpected reduction in LID, 50% in these exemplary tests.

(36) It will be understood by one of ordinary skill in this art that the one-week sunlight exposure to simulate in-use operation is relatively short, and that the LID is known to increase over time. Indeed, test Wafer # C, Series I, exhibited not only no LID, but an improvement over its initial SCE as a result of HILR treatment. That is, the 136.9% reduction in LID may be interpreted as not only no LID effect during use, but indeed, improvement in SCE during operation. Thus, with longer sunlight exposure, the reduction in LID as a result of the inventive HILR method of wafer treatment will have an even greater impact with a more substantial improvement in SCE over the useful life of the wafers in a solar cell array. The Test Series II shows that the inventive process can be integrated into a wafer processing line, such as a metallization furnace, and treat wafers at a rate matching the rate of exit of the wafers from the furnace firing/quench zones.

INDUSTRIAL APPLICABILITY

(37) It is clear that the inventive HILR treatment apparatus and methods of this application has wide applicability to the solar cell processing industry, namely to LID reduction, whether through BOC formation prevention, BOC deactivation, or BOC passivation, and to restoration of the solar energy conversion efficiency of solar cell wafers back or close to original values, and that the rate of HILR treatment can match wafer firing furnace output. Thus, the inventive system has the clear potential of becoming adopted as the new standard for apparatus and methods of LID reduction in the solar cell wafer processing industry.

(38) It should be understood that various modifications within the scope of this invention can be made by one of ordinary skill in the art without departing from the spirit thereof and without undue experimentation. For example, the ELS high-intensity light modules can have a wide range of types, designs and locations in the integrated processing line to provide the full-spectrum functionalities at in the range of intensity (3-10 Sols) disclosed herein. This invention is therefore to be defined by the scope of the appended claims as broadly as the prior art will permit, and in view of the specification if need be, including a full range of current and future equivalents thereof.

(39) Parts List (This Parts List is provided as an aid to Examination and may be canceled upon allowance)

(40) TABLE-US-00003 10 Inventive solar cell wafer processing system 12 Wafers 13 transport conveyor 14 UV pre-treatment 16 Doper module for P/B doping 18 Diffusion Furnace 20 ARC coating apparatus 22 Optional B doping 24 A, B Hi-intensity full-spectrum ELS-containing HILZ 26 Printers 28 a, b, c Hi Intensity IR Metallization Furnace 30, U, L Hi-intensity full-spectrum ELS-containing HILZ 32 Annealer 34 Burn out zone exhaust 36 Peak Firing Zone exhaust 38 Power supply & cooling system 40 Water/air cooling inputs/outputs 42 Lamp head 44 Bell housing of LEP 30U 46 Lower side walls/shroud 48 Quartz window 50 Platen or resistance coil heater 52 LEP RF/plasma emitter 54 Reflector 56 High reflectance coating 58 H.sub.2Oxidizer 60 Lamp Assys of LEP Zone B 62 Upper housing 64 Fans a-d 66 Lower housing 68 Central exhaust duct 70 Plasma drivers 72 Emitter bulbs 74 Collimator tubes 76 Collimated light 78 Shadow masks, e.g., slotted metal 82 Lands in metal, or lines on glass of shadow mask 84 Slots in metal or unlined glass areas of shadow mask 86 Radiation shield (wire mesh or perforated metal sheet) 88 Bottom surface of shadow mask 90 Top surface of wafer 92 “Light ON” interval 94 “Light OFF” interval 96 98 100 102 104 106 108 110 112 114 116 T direction of wafer transport travel through Process Zone PLH Platen heater (or equivalent, resistance coil heater) F.sub.I Forming gas input F.sub.O Forming gas output IR.sub.L High-intensity IR lamp BOC Boron-Oxygen Complex BOZ Burn-out zone PH Preheat zone FZ Firing zone QZ Quench zone LEP A Light Emitting Plasma Zone A LEP B Light Emitting Plasma Zone B WPZ Wafer Processing zone LL Lift line I Input O Output B/P or P/B, Boron/Phosphorous