Method for protecting memory against unauthorized access

Abstract

A method of protecting software for embedded applications against unauthorized access is disclosed. Software to be protected is loaded into a protected memory area and access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area only either from within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

Claims

1. An electronic device comprising: an address decoder configured to divide an address space of a memory into a protected area that includes a first portion and a second portion and into a non-protected area; and access control circuitry coupled to the address decoder and configured to: permit a first instruction fetched from the non-protected area to access the first portion of the protected area without permitting access of the second portion of the protected area; and permit a second instruction fetched from the first portion of the protected area to access the second portion of the protected area.

2. The electronic device of claim 1, wherein the protected area includes a range of addresses, the first portion is a first subset of the range of addresses, and the second portion is a second subset of the range of addresses, wherein the first and second subsets of the range of addresses do not overlap.

3. The electronic device of claim 2, wherein addresses in the second subset are higher than addresses in the first subset.

4. The electronic device of claim 1, further comprising at least one interface, the at least one interface being one of a test interface, a direct memory access interface, or an emulation interface, and wherein the access control circuitry is configured to prevent read and write operations initiated via the at least one interface from accessing the protected area.

5. The electronic device of claim 1, wherein the address decoder is configured to provide a first signal to the access control circuitry indicating whether an instruction selects an address within the protected area to access.

6. The electronic device of claim 5, wherein the address decoder is configured to provide a second signal indicating whether an instruction has been fetched from within the first portion of the protected area.

7. The electronic device of claim 6, wherein the access control circuitry is configured to assert a grant signal when the first signal and the second signal are asserted.

8. The electronic device of claim 1, wherein: the address decoder configured to divide the address space of the memory further into an auxiliary area; and the access control circuitry is configured to permit a third instruction fetched from the second portion of the protected area to access the auxiliary area.

9. The electronic device of claim 8, wherein the access control circuitry is configured to permit read and write access of the auxiliary area by the third instruction.

10. The electronic device of claim 8, wherein a range of addresses of the auxiliary area is not contiguous with a range of addresses of the protected area.

11. The electronic device of claim 1, wherein the access control circuitry is configured to: permit read, write, and execute access of the first portion of the protected area by the first instruction; and permit read, write, and execute access of the second portion of the protected area by the second instruction.

12. An electronic device comprising: a memory including an address space; an address decoder coupled to the memory and configured to divide the address space into a first non-protected area having a first address range, a second non-protected area having a second address range, a first protected area having a third address range, and a second protected area having a fourth address range; and access control circuitry coupled to the address decoder and configured to: permit a first instruction fetched from the first non-protected area to access the first protected area without permitting access of the second protected area; permit a second instruction fetched from the first protected area to access the second protected area; and permit a third instruction fetched from the second protected area to access the second non-protected area.

13. The electronic device of claim 12, wherein: the first and second address ranges are not contiguous; and the third and fourth address ranges are contiguous.

14. The electronic device of claim 13, wherein the first and second address ranges are separated by at least the contiguous third and fourth address ranges.

15. The electronic device of claim 13, wherein: addresses of the second address range are higher than addresses of the first address range; and addresses of the fourth address range are higher than addresses of the third address range.

16. The electronic device of claim 12, wherein the access control circuitry is configured to permit read, write, and branch access to the second non-protected area by the third instruction.

17. The electronic device of claim 12, wherein: the address decoder is configured to further divide the address space into an auxiliary memory area; and the access control circuitry is configured to permit a fourth instruction fetched from the second protected area to access the auxiliary memory area.

18. The electronic device of claim 12, further comprising at least one input/output interface, wherein the access control circuitry is configured to prevent read and write operations initiated via the at least one input/output interface from accessing the first and second protected areas.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

(2) FIG. 1 is a schematic diagram of a memory including a protected area including contents to which access is restricted in accordance with an embodiment of this disclosure;

(3) FIG. 2 is a schematic diagram of a state machine model representing operation of sentinel logic circuitry in accordance with an embodiment of this disclosure;

(4) FIG. 3 is a circuit diagram of exemplary sentinel logic circuitry in accordance with an embodiment of this disclosure;

(5) FIG. 4 is a circuit diagram of an exemplary address decoder in accordance with an embodiment of this disclosure;

(6) FIG. 5 is a block diagram of a logic access control circuit with three sentinel logic circuits in accordance with an embodiment of this disclosure.

DETAILED DESCRIPTION

(7) One or more specific embodiments of the present disclosure are described below. These embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions are made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such development efforts might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

(8) FIG. 1 illustrates a typical memory 100 of a programmed device such as a microcontroller. Memory has a non-protected bottom area 101. On top of bottom area 101, memory 100 has a protected memory area 110 which consists of a Z_area 111 and an area storing protected content 113 at higher memory addresses than Z_area 111. Z_area 111 contains pointers to address locations within protected content 113. Protected content 113 in turn contains software (SW) representing a valuable content to be protected from unauthorized access. At memory addresses above protected range 110, memory 100 typically contains a non-protected top area 121.

(9) Optionally, a separate auxiliary area 130 can be reached by read and read/write accesses from protected content 113 and is thus tied into the entire protected memory area 110.

(10) The left-hand side of FIG. 1 (“YOU CAN:”) notes permitted access routes between various memory areas indicated by arrows. Annotations on the arrows denote permitted read, write, execute and branch instructions associated with that access. Instructions within non-protected bottom area 101 may read, write or execute into Z_area 111. Instructions within Z_area 111 may read, write or execute into protected content 113. Instructions within protected content 113 may read, write or branch into non-protected top area 121. Instructions within protected content 113 may read or write into auxiliary area 130.

(11) The right-hand side in FIG. 1 (“YOU CAN NOT:”) notes denied access routes between various memory areas indicated by arrows. Instructions within non-protected bottom area 101 may not read, write, or execution into protected content 113. Operations within a JTAG test interface, a direct memory access (DMA) or an emulation unit (EMU) may not read or write into Z_area 111, protected content 113 or auxiliary area 130.

(12) FIG. 2 illustrates a state diagram of the inventive method in accordance with the present disclosure. The sentinel logic circuitry detailed below contains a flip-flop that is used to implement the two status signal states: Outside 201 and Inside 202. Outside 201 indicates that code execution is done from outside of a protected memory area. Inside 202 indicates that code execution is done from within a protected memory area.

(13) FIG. 2 shows that, when the current state is Outside 201, to get from Outside 201 to Inside 202 requires a fetch from Z_area 111 via path 211. After this, consecutive fetches from inside the whole protected range 110 (including Z_area 111) via path 212 and fetches from inside auxiliary area 130 via path 213 can be performed. When the current state is Inside 202, a first fetch from outside the protected range via path 214 causes a change to Outside 201. When the current state is Outside 201, fetches from outside the protected range 110 are permitted via path 215. In this example, the system may be initialized (e.g., on power up) to Inside 202 via path 216 by an initialization signal Init. This starts up the system from within a protected area. In other cases, initializing the system to Outside 201 on power up may be more beneficial.

(14) FIG. 2 illustrates that any fetch from outside of the protected range results in a status signal Outside and any fetch from inside of the protected range, or the auxiliary area tied into the protected area, results in a status signal Inside. However, a fetch from Z_area 111 within protected range 110 changes the status signal from Outside to Inside.

(15) FIG. 3 illustrates sentinel logic circuitry 300. Sentinel logic circuitry 300 includes flip-flop 310 and a number of logic gates including OR gate 301, AND gate 302, AND gate 303, OR gate 304, OR gate 305, AND gate 306, AND gate 307, and OR gate 308. Flip-flop 310 has an output Q that issues a signal PrivAcc which is assimilated with the status signal in FIG. 2. A low output PrivAcc signals an Outside 201 condition and a high output PrivAcc signals an Inside 202 condition.

(16) The following signals are used or issued by the sentinel logic circuit in FIG. 3:

(17) Init: initializes circuit after reset;

(18) Enable: enables protection circuit;

(19) MCLK: main clock of CPU in a programmed device;

(20) Fetch: High on fetch access of the central processing unit (CPU) of the system;

(21) Range: High when protected address range is selected, usually on a module select;

(22) Auxiliary: High when the fetched address is within a second address range that is assigned to the Range. This signal is used for protected RAM 130 that is assigned to the code executed from Range or protected peripherals. This signal is grounded low if only a single program memory block is to be protected.

(23) Z_area: High when Protection is bypassed, usually on Z_area 113 (bottom address area) of protectable memory 110;

(24) PrivAcc: Signals that fetch was done from within protected memory 110. Usually this signal is OR'ed together with other PrivAcc signals to generate a final privilege signal for a peripheral/memory area.

(25) Grant: High when access to memory area is granted; and

(26) Violation: High on access violation to protected memory area.

(27) The state of flip-flop 310 is preset via OR gate 301. A high Init signal indicating initialization of the system sets flip-flop 310 to the Inside status via OR gate 301. A low Enable signal indicating protection is enabled sets flip-flop 310 to the Inside status via an inverting input of OR gate 301.

(28) Flip-flop 310 is clocked to enable transitions via the output of AND gate 302. AND gate 302 is high when the clock MCLK is high and FETCH is high indicating a memory fetch by the CPU.

(29) The signals Range and Z_area are preferably provided by an address decoder described below in conjunction with FIG. 4. While it is possible to use an address comparator, an address decoder has significant advantages in terms of reduced complexity and power consumption.

(30) FIG. 4 is an example of address decoder 400. Address decoder 400 includes a multiple input AND gate 401. In the example of FIG. 4, AND gate 401 receives inputs of most significant address bits Ax, Ax+1, Ax+3 and Ax+3 to four respective inputs. The second and fourth inputs are inverting inputs. In this example, the output Range of AND gate 401 is high for a bit pattern “1010” and low otherwise.

(31) Returning to FIG. 3, a high Z_area value combined with a high Range value supplies a high value to the D-input of flip-flop 310 via AND gate 303 and OR gate 304. The output PrivAcc of flip-flop is fed back to the D-input via OR gate 304 and AND gate 306 when the signal Range or the signal Auxiliary is high as set by OR gate 305. Accordingly, flip-flop 310 latches an Inside condition once a fetch into Z_area 111 occurs. This remains as long as further fetches occur from inside of the protected memory area. OR gate 304 also generates a Grant signal when the address is within the protected Range and within the Z_area (as determined by AND gate 303) or the address fetch is within the Range or the Auxiliary area as determined by OR gate 305 and no grant signal is generated by OR gate 304 or flip-flop 310 is in the Inside condition as determined by the inverting input of AND gate 307. Possible responses to a Violation signal are a system reset or branching to an interrupt that calls a service routine.

(32) In a typical application more than one protected memory area may be used. FIG. 5 shows a combination circuit 500 including three sentinel logic circuits S1 501, S2 502 and S3 503. Each sentinel logic circuit 501, 502 and 503 is associated with one out of three different protected memory areas which can be combined or nested. Each sentinel logic circuit 501, 502 and 503 has a corresponding Range signal (R1, R2 and R3) and a corresponding Z_area signal (Z1, Z2 and Z3). Each sentinel logic circuit 501, 502 and 503 may be configured as shown in FIG. 3 to issue a corresponding Grant signal and Violation signal (not labeled in FIG. 5). Each sentinel logic circuit 501, 502 and 503 may be configured as shown in FIG. 3 to issue a corresponding status signal PA1, PA2 and PA3. The status signals PA1, PA2 and PA3 (each signaling an Inside or Outside condition) are input to OR gate 510. The output of OR gate 510 is a signal PrivAcc that signals an Inside condition when high and an Outside condition when low. This is similar to the case of a single protected memory area.

(33) While the specific embodiments described above have been shown by way of example, it will be appreciated that many modifications and other embodiments will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing description and the associated drawings. Accordingly, it is understood that various modifications and embodiments are intended to be included within the scope of the appended claims.