A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

A processing condition specifying method that includes Steps S31, S32, and S33. In Step S31, a prediction thickness information piece containing prediction values of thicknesses after processing on the substrate W is calculated for each of a plurality of recipe information pieces based on measurement thickness information containing measurement values of thicknesses of the substrate W. In Step S32, the prediction thickness information pieces each calculated for a corresponding one of the recipe information pieces are evaluated according to a prescribed evaluation method and a prediction thickness information piece is selected from among the prediction thickness information pieces. In Step S33, a recipe information piece corresponding to the selected prediction thickness information piece is specified. The measurement values contained in the measurement thickness information indicate a thickness of the substrate W measured before processing on the substrate W.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

The present invention provides a means capable of sufficiently removing a residue containing inorganic oxide abrasive grains present on the surface of a polished object to be polished containing silicon nitride. One aspect of the present invention relates to a surface treatment method for reducing a residue containing inorganic oxide abrasive grains on a surface of a polished object to be polished containing silicon nitride using a composition for surface treatment, wherein the composition for surface treatment contains a zeta potential adjusting agent having a negatively charged functional group and having a viscosity of an aqueous solution having a concentration of 20% by mass at 25° C. of 10 mPa.Math.s or more and a dispersing medium, and the surface treatment method includes controlling a zeta potential of the silicon nitride and a zeta potential of the inorganic oxide abrasive grains each to −30 mV or less using the composition for surface treatment.

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

The present disclosure relates to the field of semiconductor packaging processes, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with an exposed conductive structure; forming a passivation layer on the surface of the semiconductor substrate and a surface of the exposed conductive structure; etching the passivation layer to form a recess, where a bottom of the recess exposes one end of the conductive structure; forming an adhesion layer on a surface of the recess; and etching to form a hole in the bottom of the recess.

An etching method is provided. In the etching method, a protective film-forming gas including an amine gas is supplied to a substrate having a surface on which a first film and a second film are formed, the first film and the second film having respective properties of being etched by an etching gas, and a protective film is formed to cover the first film such that the first film is selectively protected between the first film and the second film when the etching gas is supplied. Further, the second film is selectively etched by supplying the etching gas to the substrate after the protective film is formed.

The present invention addresses the problem of providing: a polishing pad that is long-lasting, has a high polish rate, and is capable of producing a high degree of flatness on polished articles; and a method for manufacturing the polishing pad. The solution provided is to eliminate a sea component from a non-woven fabric that includes a binder fabric and a sea-island type composite fiber composed of the sea component and an island component, the island component having a diameter of 10-2500 nm, and to add a polymer elastic body to the non-woven fabric.