Abstract
A method of manufacturing a component carrier includes: (i) embedding at least one carrier plate in a core; (ii) forming a stack on the at least one carrier plate, wherein the stack comprises at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; (iii) thereafter removing the at least one carrier plate from the stack. A corresponding hybrid core and a corresponding semi-finished product each comprise analogous features.
Claims
1. A method of manufacturing a component carrier, the method comprising: embedding at least one carrier plate in a core; forming a stack on the at least one carrier plate, wherein the stack comprises at least one electrically conductive layer structure and/or at least one electrically insulating layer structure; thereafter removing the at least one carrier plate from the stack.
2. The method of claim 1, wherein a plurality of carrier plates are embedded in the core.
3. The method of claim 2, wherein two carrier plates of the plurality of carrier plates are separated by a portion of the core.
4. The method of claim 1, wherein the at least one carrier plate is attached to the core by an adhesive.
5. The method of claim 1, wherein the core and the at least one carrier plate form part of a panel, by means of which a plurality of component carriers can be manufactured.
6. The method of claim 1, wherein the at least one carrier plate comprises a release layer at which the stack is removed from the at least one carrier plate and/or wherein the at least one carrier plate comprises a seed layer, which is configured to facilitate the formation of the stack on the at least one carrier plate.
7. The method of claim 1, wherein the stack is configured as a redistribution layer for a component mounted to the stack.
8. The method of claim 7, wherein the redistribution layer enlarges the footprint of the component.
9. The method of claim 1, wherein the at least one carrier plate comprises a glass plate and/or a ceramic plate and/or a plastic plate.
10. The method of claim 1, wherein the at least one carrier plate has a surface roughness Ra of not more than 450 nm and/or wherein at least one carrier plate has a thickness of at least 0.5 mm.
11. The method of claim 1, wherein the method comprises surface mounting a component on the stack before removing the at least one carrier plate.
12. The method of claim 11, wherein the method comprises overmolding the component before removing the at least one carrier plate.
13. The method of claim 1, wherein the method comprises exposing part of an electrically conductive layer on the at least one carrier plate by patterning an electrically insulating layer on the electrically conductive layer.
14. The method of claim 13, wherein the method comprises applying electrically conductive material selectively on the exposed part of the electrically conductive layer.
15. A hybrid core for manufacturing a component carrier, the hybrid core comprising: a core; and at least one carrier plate embedded in the core, wherein the carrier plate is configured so that a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure can be formed on the at least one carrier plate.
16. The hybrid core of claim 15, wherein the at least one carrier plate is a glass plate.
17. The hybrid core of claim 15, wherein a seed layer is provided on the at least one carrier plate.
18. The hybrid core of claim 17, wherein the seed layer has a thickness smaller than 0.6 μm.
19. The hybrid core of claim 15, wherein the at least one electrically insulating layer structure comprises at least one of the group of an EBF layer structure, a PID layer structure, a further EBF layer structure and an SR layer structure.
20. A semifinished product for manufacturing a component carrier, the semifinished product comprising: a core; and at least one carrier plate embedded in the core, wherein the carrier plate is configured so that a stack comprising at least one electrically conductive layer structure and/or at least one electrically insulating layer structure can be formed on the at least one carrier plate; and a stack on the at least one carrier plate, wherein the stack comprises at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, wherein the at least one electrically insulating layer structure comprises at least one of the group of an EBF layer structure, a PID layer structure, a further EBF layer structure and an SR layer structure.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0107] FIG. 1 shows a cross-sectional side view of a semifinished product comprising a stack attached to a hybrid core according to an exemplary embodiment of the disclosure.
[0108] FIG. 2 shows a layered structure of a carrier plate according to an exemplary embodiment of the disclosure.
[0109] FIG. 3 shows a top view of a hybrid core according to an exemplary embodiment of the disclosure.
[0110] FIG. 4, FIG. 5, and FIG. 6 each show a component carrier, which has been manufactured using a method according to an exemplary embodiment of the disclosure.
[0111] FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, FIG. 19, FIG. 20, FIG. 21, FIG. 22, FIG. 23, FIG. 24, FIG. 25, FIG. 26, FIG. 27, FIG. 28, FIG. 29, FIG. 30, FIG. 31, FIG. 32, and FIG. 33 show structures obtained during manufacture of a component carrier using a hybrid core according to an exemplary embodiment of a method of manufacture.
[0112] FIG. 34 and FIG. 35 illustrate a step of bonding a core to a carrier plate according to an exemplary embodiment of the disclosure.
[0113] FIG. 36 and FIG. 37 illustrate a step of bonding a core to a carrier plate according to an exemplary embodiment of the disclosure.
[0114] FIG. 38 shows a cross-sectional side view of an interface between a core and a carrier plate according to an exemplary embodiment of the disclosure.
[0115] FIG. 39 shows a cross-sectional side view of a hybrid carrier according to an exemplary embodiment of the disclosure.
DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS
[0116] The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs. For the sake of clarity and comprehensibility, reference signs are sometimes omitted for those features, for which reference signs have already been provided in earlier figures.
[0117] Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the utility model have been developed.
[0118] A fundamental idea of the disclosure is to provide a carrier plate, in particular a glass carrier, for chip last fan-out panel level packaging (FOPLP), wherein present substrate processes and formats can be used. As an example, a HRDP glass core from Mitsui Co. could be used to this purpose. For each quadrant of the panel, a separate carrier plate could be used, wherein the carrier plates are embedded in a core, in particular a FR4 core. One or more redistribution layers (RDL) are prepared on the carrier plate using a present or conventional substrate process. This is used for packaging assembly. After component or die assembly and mold process, i.e., overmolding of the component, the carrier plate is detached and a seed metal layer on the detached side is recessed to expose a metal ball grid array (BGA) pad. Surface finishing, e.g., organic solderability preservative (OSP) finish, is applied after the recessing. Finally, each assembled unit is singulated. Also, another component or die could be assembled on the detached side to bridge die to die. This may provide more design freedom for system-in-package (SIP) configuration.
[0119] For example, glass may be considered to be a promising material for manufacturing redistribution layers. Glass may provide a relatively flat and smooth surface with good dimensional stability during thin redistribution layer processing and assembly. However, glass panels may not be applicable in present substrate processing, e.g., conventional FR4 substrate process such as an SAP process, because glass easily breaks. To profit from the advantages of glass as a carrier, while still employing conventional substrate processes, a glass carrier plate embedded in a core could be used. One or more thin redistribution layers for chip/component last FOPLP may be achievable in this way.
[0120] FIG. 1 shows a cross-sectional side view of a semifinished product 100 for manufacturing a component carrier 101. The semifinished product comprises a hybrid core 110 having a core 111 and having two carrier plates 120 embedded in the core 111. The semifinished product 100 also comprises a stack 102 on both carrier plates 120, wherein the stack 102 comprises a plurality of electrically conductive layer structures 103 and a plurality of electrically insulating layer structures 104.
[0121] In the hybrid core 110, small gaps 131 are formed between the core 111 and the carrier plates 120. These gaps 131 are filled with an adhesive 130 in order to attach the carrier plates 120 to the core 111. The core 111 consists of a core base layer 113 having a respective core metal layer 112 attached to each of the main surfaces of the core base layer 113. Each of the carrier plates 120 consists of a base layer 122 to which a seed layer 121 is attached at the side of the base layer 122 on which the stack 102 is arranged. Beneath the hybrid core 110, one or more electrically conductive layer structures 103 and/or one or more electrically insulating layer structure 104 may be arranged, for example an epoxy-based build-up film (EBF) layer 106 and a metal layer.
[0122] The stack 102 is formed continuously over the whole hybrid core 110. In the order in which the stack 102 is arranged on the carrier plate 120, the stack 102 comprises an EBF layer structure 106, a PID (photoimageable dielectric) layer structure 107, a further EBF layer structure 106, and an SR (solder resist) layer structure 108. Between those electrically insulating layer structures 104, respective electrically conductive layer structures 103 are arranged. Furthermore, the electrically conductive layer structures 103 are connected by vias 105 extending through the electrically insulating layer structures 104. At the top of the stack electrical contacts 109 are exposed in an electrically insulating layer structure 104, here the SR layer structure 108. From the stack 102, component carriers 101 will eventually be singulated. The electrical contacts 109 may be used for contacting a component mounted to the stack 102 or component carrier 101.
[0123] FIG. 2 shows the layered structure of a carrier plate 120. On a base layer 122, several de-bonding function layers are arranged, which include one or more release layers 223. Specifically, in the order, in which they are arranged on the base layer 122, the de-bonding function layers comprise first a metal layer, then a further metal layer, which serves as a first release layer 223, and finally an inorganic layer, which serves as a second release layer 223. Between the first and second release layers 223, a releasing interface is arranged indicated by the horizontal black line.
[0124] On the de-bonding function layers, one or more seed function layers are arranged. The seed function layers include a seed layer 121, which may be made of copper and may for example be 0.3 μm thick. The seed function layers may also include a titanium layer of, e.g., 0.1 μm thickness. The seed layer 121 may extend over one or more of the side surfaces of the carrier plate 120 laterally covering the whole stack of de-bonding function layers and seed function layers as well as part of the base layer 122 (not shown). Such a side edge of the seed layer may attach the various function layers to the base layer 122. Only when the side edge is removed, may the seed layer 121 be detachable from the base layer 122 at the releasing interface.
[0125] The base layer 122 may be a glass panel. The de-bonding function layers and the seed function layers, in particular the release layers 223 and the seed layer 121, may be applicable to the base layer 122 by sputtering. These function layers may have a total thickness of 0.6 μm, in particular less than 0.6 μm.
[0126] FIG. 3 shows a hybrid core 110 comprising four rectangular carrier plates 120. The carrier plates 120 are embedded in a core 111 such that ridges 315 of the core 111 separate the carrier plates 120 from each other and such that an outer frame 314 of the core 111 surrounds the carrier plates 120. As a result, each carrier plate 314 forms a quarter panel of the hybrid core 110.
[0127] FIG. 4 to FIG. 6 each show a component carrier 101, which has been manufactured according to an exemplary embodiment of the disclosure. Components 440 have been attached to a stack 102 comprising electrically conductive layer structures 103 and electrically insulating layer structures 104. The electrically insulating layer structures 104 comprise an EBF layer structure 106, a PID layer structure 107, a further EBF layer structure 106, and an SR layer structure 108. Electrical contacts 109 are exposed in the SR layer structure 108. Solder balls 442 electrically connect the electrical contacts 109 with components 440, which are mounted to the stack 102. The components 440 are encapsulated by an overmolding 441.
[0128] By the methods described in this patent application, various electronic packages comprising a stack 102 and one or more components 440 may be built. For example, on the main surface of the stack 102 opposite the component(s) 440, solder balls 442 may be applied for electrically contacting the package. Also, a further component 440 may be mounted beneath the package. This further component may also be encapsulated by an overmolding 442. Further electrically conductive and/or electrically insulating layer structures 103, 104 may be arranged beneath the package.
[0129] FIG. 7 to FIG. 33 show structures obtained during manufacture of a component carrier using a hybrid core 110.
[0130] In FIG. 7, a core 111 of 1.0 mm thickness is provided. The core 111 comprises a core base layer 113 with a respective core metal layer structure 112 attached to each main surface of the core base layer 113. In FIG. 8, through-holes are routed in the core. In FIG. 9, a respective carrier plate 120, e.g., a glass carrier with a metal layer 121 attached to one side, is arranged in each of these through-holes. Thereby, a hybrid core 110 is formed. In FIG. 10, a temporary carrier 1050, e.g., a carrier tape, is attached to the hybrid core 110, in particular the core 111 and the carrier plates 120, with the metal layer 121 facing and/or adjacent to the carrier tape 1050. Gaps 131 result between core 111 and the carrier plates 120.
[0131] In FIG. 11, a layer comprising an adhesive substance 130 such as a prepreg layer is applied to the side of the hybrid core 110 opposite the side with the carrier tape 1050. The layer is molded and cured such that the adhesive 130 of the layer, in particular resin, fills the gaps 131 and attaches the carrier plates 120 to the core 111. An EBF layer structure 106 is arranged on the layer comprising the adhesive 130. In FIG. 12, the temporary carrier 1050 is removed after the adhesive 130 has been cured.
[0132] As an alternative to the process depicted in FIG. 11 and FIG. 12, the adhesive 130 is applied not in terms of a layer, but in terms of a liquid, which is directly injected into the gaps 131 and is then cured. Again, the temporary carrier 1050 is removed, once the adhesive 130 has been cured.
[0133] The step depicted in FIG. 14 continues the process of FIG. 11 and FIG. 12 or the process of FIG. 13. An insulating layer structure 104, in particular an EBF layer structure 106, is attached, in particular laminated, to the hybrid core 110, in particular to the core 111 and the carrier plates 120, with the metal layer 121 facing and/or adjacent to the EBF layer structure 106. The EBF layer structure 106 may be laminated on top of the metal layer 121. The EBF layer structures 106 on opposite sides of the hybrid core 110 may be laminated subsequently or both at the same time.
[0134] In FIG. 15, holes are drilled, in particular laser drilled, through EBF layer structure 106 so that the metal layer 121 underneath can be contacted, e.g., for forming a ball grid array (BGA). Alternatively, instead of the EBF layer structure a photoimageable dielectric (PID) may be used and vias may be formed by a lithographic process. In FIG. 16, an electrically conductive layer structure 103 is formed on the EBF layer structure 106. Also, the holes are at least partially filled with an electrically conductive material, e.g., copper, so that vias are formed for electrically contacting the metal layer 121 from the electrically conductive layer structure 103. As a result, a first redistribution layer is formed. In FIG. 17 to FIG. 19, this process is repeated twice, whereby two further redistribution layers are formed. The electrically insulating layer structure 104 may for example be a PID layer structure 107 or a further EBF layer structure 106. A PID layer structure 107 may be laminated and/or coated.
[0135] The steps of FIG. 20 to FIG. 22 show the formation of an image for die connection using a solder resist layer structure 108. Alternatively, a PID layer structure could be used. In FIG. 20, a solder resist (SR) layer structure 108 is applied to the stack, in particular by lamination. Electrical contacts 109 can be formed by a plasma etch step as shown in FIG. 21. Alternatively, electrical contacts 109 can be formed by lithographic imaging of the SR layer structure 108 as shown in FIG. 22. The electrical contacts 109 may be exposed by forming holes through the SR layer structure 108. Subsequently, a surface finished may be applied (not shown), e.g., an ENEPIG surface finish.
[0136] FIG. 23 depicts a resulting semifinished product 100 with a stack 102 attached to a hybrid core 110. In FIG. 24, different portions of the hybrid core 110 and corresponding portions of the stack are separated from each other by a routing step 2460. The hybrid core 110 is separated in regions, where the core 111 is located, rather than in regions, where the carrier plates 120 are located. Each portion of the hybrid core 110 comprises a single carrier plate 120 and surrounding parts of the core 111. This process results in semifinished products 100 as depicted in FIG. 25, one for each carrier plate 120. These semifinished products 100 comprise a single carrier plate 120 and a stack 102 built on the carrier plate. Solder balls 442 are mounted on the electric contacts 109.
[0137] FIG. 26 shows the semifinished product of FIG. 25 having two components 440 mounted to the stack 102 and electrically connected to the stack 102 by means of the solder balls 442, in particular using bumps and an underfill. In the step of FIG. 27, the components 440 are at least partially encapsulated by an overmolding 441. The overmolding 441 attaches directly to the stack 102 providing further stability.
[0138] In the step of FIG. 28, all regions of the semifinished product 100 of FIG. 27, where the core 111 is located are removed by cutting 2861, in particular by laser cutting and/or saw cutting, such that only regions with the carrier plate 120 remain. In the step of FIG. 29, the carrier plate 120 is separated from the stack 102. It may for example be separated at a release layer 223 (not shown) or a releasing interface of the carrier plate 120. The releasing may be possible because the core 111 has been cut off, which does not comprise a release layer 223 or a releasing interface.
[0139] FIG. 30 shows a component carrier 101 or an array of component carriers 101, where the metal layer 121, in particular a Ti/Cu layer of the carrier plate 120, has been etched. An array of component carriers 101 may now or at a later step be singulated, i.e., separated into single component carriers 101. In the step of FIG. 31, solder balls 442 or alternatively copper pillars have been attached for top side structuring. Also, an organic solderability preservative (OSP) may be applied. In the step of FIG. 32, a further component 440 may be attached at a side of the component carrier opposite the side, where components were previously attached. Also, further solder balls 442 or copper pillars may be arranged to contact the component carrier. In particular, TCP bonds may be implemented. Finally, in the step depicted in FIG. 33, upper side structuring may be carried out. For example, the further component 440 may be encapsulated by a further overmolding 441. Also, further electrically conductive layer structures 103 and/or further electrically insulating layer structures 104 may be applied. Redistribution layers may be formed on the upper side, i.e., the side, on which the carrier plate was previously attached. Electrical contacts 109 may be formed on the upper side. By this process compact packages comprising electronic components may result.
[0140] FIG. 34 to FIG. 38 show two processes how a hybrid core 110 may be assembled from a core 111 and at least one carrier plate 120.
[0141] The first bonding method as depicted in FIG. 34 and FIG. 35 shows adhesive filling, in particular resin filling (cp. also FIG. 13). First, a step of direct dispensing of an adhesive such as a mold resin or an epoxy resin is carried out and second, a step of capillary filling is carried out. FIG. 34 shows a top view of a hybrid core 110 and FIG. 35 a bottom view of the same hybrid core 110. In the bottom view, a temporary carrier 1050, in particular a carrier tape, is visible, to which the core 111 and the carrier plate 120 are attached. The carrier tape 1050 may seal the gaps 131 between core 111 and carrier plate 120 from beneath during assembly of the hybrid core. In the top view of FIG. 34, dispensing holes 3470 are visible, in which the adhesive is dispensed. Pins 3471 may guide and/or obstruct the flow of the adhesive. The adhesive then fills at least partially, in particular fully, the gaps 131 and/or capillaries between the carrier plate 120 and the core 111. The width of the gaps and/or capillaries may be between 0.01 and 0.20 mm.
[0142] The second bonding method as depicted in FIG. 36 to FIG. 38 shows adhesive inserting, in particular prepreg inserting (cp. also FIGS. 11 and 12). A layer comprising an adhesive 130, e.g., a prepreg layer, is laminated on top of the hybrid core, wherein the gap 131 between core 111 and carrier plate 120 is at least partially, in particular fully, filled with adhesive 130. When the adhesive is cured, the carrier plate 120 is attached to the core 111.
[0143] FIG. 36 shows a top view of the hybrid core 110 with a gap 131 separating core 111 and carrier plate 120. FIG. 37 shows a bottom view of the hybrid core 110 with a carrier tape 1050 attached to the bottom of at least part of the hybrid core 110, in particular attached to both core 111 and carrier plate 120 at a region where the gap 131 is located. The carrier tape 1050 may be an epoxy/glass fabric impregnated tape and it may be approximately 80 μm thick. It may seal the gap 131 from beneath during assembly of the hybrid core 110.
[0144] FIG. 38 is a cross-sectional side view of a region of the hybrid core 110, where a gap 131 is located. The gap 131 separates the core 111 from the carrier plate 120 and is filled with adhesive 131. The width of the gap 131 may be between 0.1 mm and 0.2 mm, in particular 0.10 mm, 0.12 mm or 0.14 mm. The carrier tape 1050 is attached to core 111 and carrier plate 120 at the region of the gap 131 and at the side of the carrier plate 120 with the metal layer 121.
[0145] FIG. 39 depicts a cross-sectional view of layers of a hybrid core 110 which are to be connected to a stack-up by lamination, in particular by hot press. In the center, a core 111, e.g., a FR-4 core of 1.05 mm thickness, is laterally attached to a carrier plate 120 by an adhesive 130. The carrier plate 120 comprises a base layer 122, e.g., a glass core of 1.0 mm thickness, and a seed layer 121, in particular a metal layer, attached to the base layer 122. On the side, where the seed layer 121 is located, further layers are attached in the following order: an EBF layer 106 of 20 μm thickness, an electrically conductive layer 103, e.g., a copper foil, a sus plate, i.e., a plate made from stainless steel, and a cushion pad. On the opposite side, i.e., where the seed layer 121 is not located, further layers are attached in the following order: three prepreg layers 3980, an electrically conductive layer 103, e.g., a copper foil, a sus plate, i.e., a plate made from stainless steel, and a cushion pad. The above-described layered structure may be useful for lamination in a hot press.
[0146] It should be noted that the term “comprising” does not exclude other elements or steps and the use of articles “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.
[0147] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.
