FABRICATION METHOD OF PACKAGE STRUCTURE
20170229319 · 2017-08-10
Inventors
Cpc classification
H01L2221/68359
ELECTRICITY
H01L21/4853
ELECTRICITY
H01L2224/1403
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L2224/81193
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2224/81191
ELECTRICITY
H01L23/3128
ELECTRICITY
H01L2924/00014
ELECTRICITY
H01L23/3178
ELECTRICITY
H01L21/486
ELECTRICITY
H01L23/49816
ELECTRICITY
H01L2224/131
ELECTRICITY
H01L2221/68345
ELECTRICITY
H01L23/49811
ELECTRICITY
H01L21/4846
ELECTRICITY
H01L23/49827
ELECTRICITY
International classification
H01L21/48
ELECTRICITY
H01L23/498
ELECTRICITY
Abstract
A method for fabricating a package structure is provided, which includes the steps of: forming a first insulating layer on a carrier; forming a dielectric body on the first insulating layer, wherein the dielectric body has a first surface formed on the first insulating layer and a second surface opposite to the first surface, and a circuit layer and a plurality of conductive posts formed on the circuit layer are embedded in the dielectric body; forming a second insulating layer on the second surface of the dielectric body, wherein the glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 250° C.; and removing the carrier. Since the glass transition temperature of the first or second insulating layer is greater than that of the dielectric body, the package structure has a preferred strength to avoid warping, thereby dispensing with a support member.
Claims
1. A method for fabricating a package structure, comprising the steps of: forming a first insulating layer on a carrier; forming a dielectric body on the first insulating layer, wherein the dielectric body has a first surface coupled to the first insulating layer and a second surface opposite to the first surface, and a circuit layer and a plurality of conductive posts formed on the circuit layer are embedded in the dielectric body; forming a second insulating layer on the second surface of the dielectric body, wherein a glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 250° C.; disposing a semiconductor element on the first insulating layer, wherein the semiconductor element is electrically connected to the circuit layer; forming an encapsulant on the first insulating layer to encapsulate the semiconductor element, wherein the encapsulant has a thickness between 20 and 180 μm; and removing the carrier.
2. The method of claim 1, wherein the conductive posts are exposed from the second surface of the dielectric body.
3. The method of claim 2, further comprising forming in the first insulating layer a plurality of first openings for exposing the circuit layer, and forming in the second insulating layer a plurality of second openings for exposing the conductive posts.
4. The method of claim 3, further comprising forming a plurality of conductive bumps on the circuit layer exposed from the first openings of the first insulating layer.
5. The method of claim 4, wherein the conductive bumps are 50 μm in height.
6-8. (canceled)
9. The method of claim 1, wherein a thickness of the first insulating layer or the second insulating layer is between 1 and 20 μm.
10. The method of claim 1, wherein the glass transition temperature of the first insulating layer and/or the second insulating layer is greater than 400° C.
11. The method of claim 1, wherein the first insulating layer and/or the second insulating layer are made of polyimide (PI), polyamide-imide (PAI) or polybenzimidazole (PBI).
12-22. (canceled)
Description
BRIEF DESCRIPTION OF DRAWINGS
[0025]
[0026]
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0027] The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those in the art after reading this specification.
[0028] It should be noted that all the drawings are not intended to limit the present invention. Various modifications and variations can be made without departing from the spirit of the present invention. Further, terms such as “first”, “second”, “on”, “a” etc. are merely for illustrative purposes and should not be construed to limit the scope of the present invention.
[0029]
[0030] Referring to
[0031] In the present embodiment, the carrier 20 is, for example, a steel board, a silicon board or a glass board and has a metal layer, such as copper, thereon.
[0032] The glass transition temperature of the first insulating layer 30 is greater than 250° C., preferably greater than 400° C.
[0033] Further, the first insulating layer 30 is made of polyimide (PI), polyamide-imide (PAI) or polybenzimidazole (PBI).
[0034] In an embodiment, referring to
[0035] Referring to
[0036] In the present embodiment, the circuit layer 31 is formed on the first insulating layer 30 and the conductive posts 33 are formed on a portion of the circuit layer 31. Then, a dielectric material is formed on the first insulating layer 30 to form the dielectric body 32 encapsulating the circuit layer 31 and the conductive posts 33. But it should be noted that there is no special limitation on the order of formation of the dielectric body 32, the circuit layer 31 and the conductive posts 33.
[0037] The dielectric body 32 can be made of, but not limited to, a molding compound material, a prepreg material or a photo-dielectric material. In another embodiment, the dielectric body 32 is made of the same material as the first insulating layer 30.
[0038] The conductive posts 33 can have a circular cylindrical shape, an elliptical cylindrical shape or a polygonal cylindrical shape.
[0039] In another embodiment, referring to
[0040] Referring to
[0041] In the present embodiment, the glass transition temperature of the second insulating layer 34 is greater than 250° C., preferably greater than 400° C.
[0042] The second insulating layer 34 can be made of polyimide (PI), polyamide-imide (PAI) or polybenzimidazole (PBI).
[0043] Referring to
[0044] In the present embodiment, a surface processing layer 37 is formed on the circuit layer 31 and a surface processing layer 37′ is formed on the conductive posts 33. The surface processing layer 37, 37′ can be made of an alloy of nickel, palladium and gold or an organic solderability preservative (OSP).
[0045] In another embodiment, referring to
[0046] According to the present invention, since the glass transition temperature of the first insulating layer 30 and/or the second insulating layer 34 is greater than 250° C., the first insulating layer 30 and/or the second insulating layer 34 cause the package structure 3 to have a preferred strength to avoid cracking or warping during high temperature processes. Therefore, the carrier 20 is removed and not used for support in subsequent processes.
[0047] Thereafter, referring to
[0048] In the present embodiment, the glass transition temperature of the encapsulant 42 is less than the glass transition temperature of the first insulating layer 30 or the second insulating layer 34.
[0049]
[0050] In an embodiment, referring to
[0051] Further, the thickness h2 of the encapsulant 42 is between 20 and 180 μm, and the height t of the conductive bumps 41 is 50 μm.
[0052] In the package structure 4, 4′, 4″, since the glass transition temperature of the first insulating layer 30 and/or the second insulating layer 34 is greater than 250° C., the carrier 20 can be removed. Therefore, the thickness h2 of the encapsulant 42 is between 20 and 180 μm.
[0053] The present invention provides a package structure 3, 3′, 4, 4′, 4″, which has: a dielectric body 32 having opposite first and second surfaces 32a, 32b; a circuit layer 31 embedded in the dielectric body 32; a plurality of conductive posts 33 formed on the circuit layer 31 and embedded in the dielectric body 32; a first insulating layer 30 formed on the first surface 32a of the dielectric body 32; and a second insulating layer 34 formed on the second surface 32b of the dielectric body 32, wherein the glass transition temperature of the first insulating layer 30 and/or the second insulating layer 34 is greater than 250° C.
[0054] The thickness of the first insulating layer 30 and/or the second insulating layer 34 can be between 1 and 20 μm.
[0055] In an embodiment, the conductive posts 33 are exposed from the second surface 32b of the dielectric body 32. The first insulating layer 30 can have a plurality of first openings 30a for exposing the circuit layer 31, and the second insulating layer 34 can have a plurality of second openings 34a for exposing the conductive posts 33. The package structure can further have a plurality of conductive bumps 41, 41′ formed on the circuit layer 31 exposed from the first openings 30a of the first insulating layer 30. The height t of the conductive bumps 41, 41′ can be 50 μm.
[0056] In an embodiment, the package structure further has a semiconductor element 40 disposed on the first insulating layer 30 and electrically connected to the circuit layer 31, and an encapsulant 42 formed on the first insulating layer 30 for encapsulating the semiconductor element 40. The thickness h2 of the encapsulant is between 20 and 180 μM.
[0057] In an embodiment, the glass transition temperature of the first insulating layer 30 and/or the second insulating layer 34 is greater than 400° C.
[0058] In an embodiment, the first insulating layer 30 and/or the second insulating layer 34 are made of polyimide, (PI), polyamide-imide (PAI) or polybenzimidazole (PBI).
[0059] According to the present invention, since the first insulating layer and/or the second insulating layer have a high glass transition temperature, the package structure has a preferred strength to avoid warping. Therefore, the final package structure does not need the carrier for support.
[0060] Further, during a high-temperature and long-time reflow process, for example, an infrared (IR) reflow process, the first insulating layer and/or the second insulating layer are not easy to soften or displace and has little deformation. Therefore, compared with the prior art, the package structure of the present invention achieves a higher alignment accuracy.
[0061] Furthermore, the first insulating layer and the second insulating layer can be used for circuit protection without increasing the thickness of the overall package structure. As such, after the semiconductor element is disposed on the first insulating layer, the encapsulant encapsulating the semiconductor element has a thickness less than 200 μm. Therefore, the package structure has a reduced thickness and is applicable in thin electronic products.
[0062] The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.