ION CONTROLLABLE TRANSISTOR FOR NEUROMORPHIC SYNAPSE DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

Disclosed is an ion controllable transistor-based neuromorphic synaptic device used for a memory and a neuromorphic computing in such a manner that a synaptic weight is analogically updated and maintained. The ion controllable transistor-based neuromorphic synaptic device includes a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.

Claims

1. An ion controllable transistor-based neuromorphic synaptic device comprising: a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.

2. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein, in response to a voltage pulse being applied to the gate area, the ion controllable transistor-based neuromorphic synaptic device analogically updates channel conductance by movement of ions present in the solid electrolyte layer.

3. The ion controllable transistor-based neuromorphic synaptic device of claim 2, wherein the ion controllable transistor-based neuromorphic synaptic device analogically updates the channel conductance by movement of ions present in the solid electrolyte layer, using a characteristic of the solid electrolyte layer in which ions are linearly and analogically distributed.

4. The ion controllable transistor-based neuromorphic synaptic device of claim 2, wherein the ion controllable transistor-based neuromorphic synaptic device analogically expresses a synaptic weight by analogically updating the channel conductance.

5. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the solid electrolyte layer comprises at least one of a sulfide-based material with high ionic conductivity and present in a solid state [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, argyrodite, lithium phosphorus sulfide (LPS), LPS+LiCl], an oxide-based material [perovskite, NASICON (Na1+xZr2SixP3−xO12, 0<x<3), LISICON (Li2+2xZn1−xGeO4), LiPON (LixPOyNz), garnet], and an ion conductive polymer [polyethylene oxide (PEO), polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), nafion (C7HF13O5S.C2F4)].

6. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the channel area, the source area, and the drain area form a semiconductor area in a structure formed in a horizontal direction or a vertical direction.

7. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the channel area comprises at least one semiconductor material of silicon (Si), germanium (Ge, SiGe), a group III-V compound, and a 2-D material including carbon nanotube, MoS2, and graphene.

8. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the source area and the drain area are formed in a form in which impurity ions are implanted into a semiconductor material forming the channel area, formed of a silicide alloy that contains at least one of Al, W, Ti, Co, Ni, Er, and Pt, or formed of at least one metal of Au, Al, Ag, Mg, Ca, Yb, Cs—ITO, Ti, Cr, and Ni.

9. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the interlayer insulating film comprises at least one material of silicon oxide (SiO.sub.2), germanium oxide (GeO.sub.2), a solid oxide film, and a low-k dielectric film capable of insulating between the gate area and the channel area, when the ion controllable transistor-based neuromorphic synaptic device updates a synaptic weight update or a transistor operation.

10. The ion controllable transistor-based neuromorphic synaptic device of claim 1, further comprising: a sacrificial insulating film formed of at least one of silicon oxide (SiO.sub.2), germanium oxide (GeO.sub.2), a solid oxide film, and a low-k dielectric film, while being provided on the source area and the drain area.

11. The ion controllable transistor-based neuromorphic synaptic device of claim 1, wherein the ion controllable transistor-based neuromorphic synaptic device is configured as a 3-terminal that includes a terminal of the gate area, a terminal of the source area, and a terminal of the drain area, or a 4-terminal that includes a body terminal with the terminal of the gate area, the terminal of the source area, and the terminal of the drain area.

12. A gate-first manufacturing method of an ion controllable transistor-based neuromorphic synaptic device, the gate-first manufacturing method comprising: depositing an interlayer insulating film, a solid electrolyte layer, and a gate area on a semiconductor substrate; patterning a portion of the interlayer insulating film, the solid electrolyte layer, and the gate area provided on a channel area that is formed on the semiconductor substrate; forming a source area and a drain area on a portion of the semiconductor substrate exposed as the patterning result, the portion of the semiconductor substrate being present at both sides of the channel area; and depositing a sacrificial insulating film on the source area and the drain area.

13. A gate-last manufacturing method of an ion controllable transistor-based neuromorphic synaptic device, the gate-last manufacturing method comprising: forming a source area and a drain area on a semiconductor substrate, a dummy gate being provided on a channel area that is formed on the semiconductor substrate; depositing a sacrificial insulating film on the semiconductor substrate; selectively removing the dummy gate; and forming an interlayer insulating film, a solid electrolyte layer, and a gate area in a space in which the dummy gate is removed.

14. A synaptic array comprising a plurality of ion controllable transistor-based neuromorphic synaptic devices, wherein each of the plurality of ion controllable transistor-based neuromorphic synaptic devices comprises: a channel area formed on a semiconductor substrate; a source area and a drain area formed at both sides of the channel area, respectively; an interlayer insulating film provided on the channel area; a gate area formed on the interlayer insulating film; and a solid electrolyte layer inserted between the interlayer insulating film and the gate area.

15. The synaptic array of claim 14, wherein the synaptic array is configured to support a parallel operation of updating a synaptic weight through a terminal of the gate area and reading the updated synaptic weight through a terminal of the drain area in each of the plurality of ion controllable transistor-based neuromorphic synaptic devices.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0036] These and/or other aspects, features, and advantages of the invention will become apparent and more readily appreciated from the following description of embodiments, taken in conjunction with the accompanying drawings of which:

[0037] FIG. 1 is a perspective view illustrating an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0038] FIG. 2A is a graph showing a measurement of a drain voltage (I.sub.D) over a gate voltage (V.sub.G) of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0039] FIGS. 2B and 2C illustrate an operation of updating channel conductance by movement of ions present in a solid electrolyte layer included in an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0040] FIG. 3 is a graph showing a weight potentiation characteristic and a weight depression characteristic of a solid electrolyte layer included in an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0041] FIG. 4 is a flowchart illustrating a gate-first manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0042] FIGS. 5A to 5D are X-Z cross-sectional views illustrating a gate-first manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0043] FIG. 6 is a flowchart illustrating a gate-last manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment;

[0044] FIGS. 7A to 7D are X-Z cross-sectional views illustrating a gate-last manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment; and

[0045] FIG. 8 illustrates a synaptic array configured as an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment.

DETAILED DESCRIPTION

[0046] Aspects and features of the disclosure and methods to achieve the same may become clear with reference to the accompanying drawings and the following example embodiments. The example embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments. Rather, the illustrated embodiments are provided as examples so that this disclosure will be thorough and complete, and are defined by the scope of the claims.

[0047] The terms used herein are to describe the example embodiments and not to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the,” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups, thereof.

[0048] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or this disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0049] Hereinafter, the example embodiments will be described in more detail with reference to the accompanying drawings. Like reference numerals refer to like elements throughout.

[0050] Also, terminologies used herein are to appropriately express example embodiments and may vary according to the intent of a user or an operator, or a custom in the field to which the disclosure pertains. Accordingly, the terminologies should be defined based on the overall contents of the present specification.

[0051] FIG. 1 is a perspective view illustrating an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment. Hereinafter, although it is described that an ion controllable transistor-based neuromorphic synaptic device 100 is in a structure formed in a horizontal direction for clarity of description, the ion controllable transistor-based neuromorphic synaptic device 100 may have a structure formed in a vertical direction in terms of integration.

[0052] Referring to FIG. 1, the ion controllable transistor-based neuromorphic synaptic device 100 according to an example embodiment may include a semiconductor substrate 110, a channel area 120, a source area 130, and a drain area 140, an interlayer insulating film 150, a gate area 160, and a solid electrolyte layer 170.

[0053] For the semiconductor substrate 110, a single wafer may be selected from among a silicon wafer, a strained silicon wafer, a germanium wafer, a strained germanium wafer, and a silicon germanium wafer and then be used.

[0054] The channel area 120 may be formed on the semiconductor substrate 110 using at least one semiconductor material of silicon (Si), germanium (Ge, SiGe), a group III-V compound, and a 2-D material (carbon nanotube (CNT), MoS2, graphene, etc.).

[0055] The source area 130 and the drain area 140 may be formed at both sides of the channel area 120, respectively, and more particularly, may be formed in a form in which impurity ions (N-type impurities such as arsenic (As), phosphorous (P), etc., or P-type impurities such as boron (B)) are implanted into a semiconductor material that forms the channel area 120, may be formed of a silicide alloy that contains at least one of Al, W, Ti, Co, Ni, Er, and Pt, or may be formed of at least one metal of Au, Al, Ag, Mg, Ca, Yb, Cs—ITO, Ti, Cr, and Ni. For example, when a semiconductor area that is the semiconductor substrate 110 including the channel area 120, the source area 130, and the drain area 140 is to be formed through impurity ion implantation, the source area 130 and the drain area 140 may be formed by providing a silicide alloy such as Al, W, Ti, Co, Ni, Er, and Pt. As another example, when the semiconductor area is to be formed using a 2-D material, the source area 130 and the drain area 140 may be formed by providing at least one metal of Au, Al, Ag, Mg, Ca, Yb, Cs—ITO, Ti, Cr, and Ni.

[0056] Here, the source area 130 and the drain area 140 need to have the same impurity ion type, and an impurity ion type of the channel area 120 may differ from the impurity ion type of each of the source area 130 and the drain area 140. Here, in a junctionless structure, the impurity ion type of the channel area 120 may be identical to the impurity ion type of each of the source area 130 and the drain area 140.

[0057] The channel area 120, the source area 130, and the drain area 140 may constitute the semiconductor area, may be formed using at least one of a silicon wafer, a germanium wafer, a group III-V compound wafer, and a 2-D material (CNT, MoS2, etc.).

[0058] The semiconductor area may be formed as an N+ type/P type/N+ type (source area 130/channel area 120/drain area 140) or a P+ type/N type/P+ type (source area 130/channel area 120/drain area 140) through impurity ion implantation. For example, the semiconductor area may be formed through an ion implantation, an epitaxial growth, or a selective epitaxial growth on the semiconductor substrate 110. When the epitaxial growth is used, the semiconductor area may be formed of at least one of silicon, strained silicon, silicon germanium, and silicon carbide.

[0059] Therefore, the semiconductor area provided in order of source area 130/channel area 120/drain area 140 may have an N+ type/P type/N+ type or a P+ type/N type/P+ type in the case of a junction structure or may have an N+ type/N+ type/N+ type in the case of a junctionless structure.

[0060] The interlayer insulating film 150 may be provided on the channel area 120, and may be formed of at least one material of silicon oxide (SiO.sub.2), germanium oxide (GeO.sub.2), a solid oxide film, and a low-k dielectric film that may insulate between the gate area 160 and the channel area 120, when the ion controllable transistor-based neuromorphic synaptic device 100 performs a synaptic weight update or a transistor operation.

[0061] The gate area 160 may be formed on the interlayer insulating film 150, and the solid electrolyte layer 170 may be inserted between the gate area 160 and the interlayer insulating film 150.

[0062] The solid electrolyte layer 170 may be formed at least one of a sulfide-based material with high ionic conductivity and present in a solid state [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, argyrodite, lithium phosphorus sulfide (LPS), LPS+LiCl], an oxide-based material [perovskite, NASICON (Na1+xZr2SixP3−xO12, 0<x<3), LISICON (Li2+2xZn1−xGeO4), LiPON (LixPOyNz), garnet], and an ion conductive polymer [polyethylene oxide (PEO), polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), nafion (C7HF13O5S.C2F4)].

[0063] Here, the solid electrolyte layer 170 may be used to change a channel conductance of the ion controllable transistor-based neuromorphic synaptic device 100. Hereinafter, the channel conductance represents conductivity of the channel area 120. That is, the ion controllable transistor-based neuromorphic synaptic device 100 including the solid electrolyte layer 170 may operate based on an operating principle of a field effective transistor (FET) in which current flows through the channel area 120 as a voltage greater than or equal to a threshold voltage applies to the gate area 160 and a specific voltage applies to the drain area 140. Further description related thereto is made below with reference to FIGS. 2A to 2C.

[0064] Also, the ion controllable transistor-based neuromorphic synaptic device 100 may further include a sacrificial insulating film 180 provided on the source area 130 and the drain area 140 and formed of at least one material of silicon oxide (SiO.sub.2), germanium oxide (GeO.sub.2), a solid oxide film, and a low-k dielectric film.

[0065] FIG. 2A is a graph showing a measurement of a drain voltage I.sub.D over a gate voltage V.sub.G of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment, and FIGS. 2B and 2C illustrate an operation of updating channel conductance by movement of ions present in a solid electrolyte layer included in an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment.

[0066] Referring to FIGS. 2A to 2C, the ion controllable transistor-based neuromorphic synaptic device 100 may change channel conductance with charge caused by movement of ions inside the solid electrolyte layer 170 that inserts into the gate area 160. Therefore, referring to the graph of FIG. 2A, the drain current I.sub.D according to the gate voltage V.sub.G may have a hysteresis curve in a counterclockwise direction ({circle around (1)}.fwdarw.{circle around (2)}.fwdarw.{circle around (3)}.fwdarw.{circle around (4)}).

[0067] For example, referring to FIG. 2B, when a positive voltage pulse is applied to the gate area 160, cations present in the solid electrolyte layer 170 move closer to the channel area 120 or anions move closer to the gate area 160. Alternatively, at the same time at which the cations move closer to the channel area 120, the anions move closer to the gate area 160. In this manner, potential near the channel area 120 increases. Accordingly, inversion of a semiconductor channel may be facilitated, which may lead to decreasing a threshold voltage and increase the channel conductance.

[0068] As another example, referring to FIG. 2C, when a negative voltage pulse is applied to the gate area 160, anions present in the solid electrolyte area 170 move closer to the channel area 120 or cations move closer to the gate area 160. Alternatively, at the same time at which the anions move closer to the channel area 120, the cations move closer to the gate area 160. In this manner, potential near the channel area 120 decreases. Accordingly, inversion of the semiconductor channel becomes difficult, which may lead to increasing the threshold voltage and decreasing the channel conductance.

[0069] The channel conductance changed and updated with charge caused by movement of ions in the solid electrolyte layer 170 may represent a synaptic weight of the ion controllable transistor-based neuromorphic synaptic device 100. That is, the ion controllable transistor-based neuromorphic synaptic device 100 may represent potentiation or depression of the synaptic weight by updating the channel conductance based on movement of ions inside the solid electrolyte layer 170.

[0070] For example, as described above with reference to FIGS. 2B and 2C, the ion controllable transistor-based neuromorphic synaptic device 100 may increase or decrease the synaptic weight that is the channel conductance. In detail, for example, referring to FIG. 2B, the ion controllable transistor-based neuromorphic synaptic device 100 may apply the positive voltage pulse to the gate area 160 to make the cations present in the solid electrolyte layer 170 move closer to the channel area 120 or to make the anions move closer to the gate area 160, thereby increasing the potential near the channel area 120 and increasing the synaptic weight represented as the channel conductance. As another example, referring to FIG. 2C, the ion controllable transistor-based neuromorphic synaptic device 100 may apply the negative voltage pulse to the gate area 160 to make the anions present in the solid electrolyte layer 170 move closer to the channel area 120 or to make the cations move closer to the gate area 160, thereby decreasing the potential near the channel area 120 and decreasing the synaptic weight represented as the channel conductance.

[0071] As described above, in the ion controllable transistor-based neuromorphic synaptic device 100, a memory operation may be implemented with movement of cations and anions present in the solid electrolyte layer 170 and the synaptic device characteristic in neuromorphic computing may be implemented by memorizing, as the synaptic weight, the change in the channel conductance caused by movements of ions.

[0072] Although it is described that the ion controllable transistor-based neuromorphic synaptic device 100 implements the synaptic device characteristic of representing the synaptic weight with the change in the channel conductance, it is provided as an example only. Since it is possible to implement spike timing dependent plasticity (STDP), short term plasticity (STP), and long term plasticity (LTP) characteristics like a synapse of a real living organism by adjusting a frequency and a width of a voltage pulse applied to the gate area 160 or by adjusting materials of the channel area 120, the solid electrolyte layer 170, and the gate area 160, it is possible to apply to a spiking neural network as well as a deep neural network.

[0073] In particular, the ion controllable transistor-based neuromorphic synaptic device 100 may linearly and analogically update the synaptic weight that is the channel conductance. Further description related thereto is made with reference to FIG. 3.

[0074] FIG. 3 is a graph showing a weight potentiation characteristic and a weight depression characteristic of a solid electrolyte layer included in an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment.

[0075] Referring to the graph of FIG. 3, the ion controllable transistor-based neuromorphic synaptic device 100 may have a large number of synaptic weight stages in a linear and analog manner through synaptic weight potentiation and depression stages. This is due to a characteristic that ions inside the solid electrolyte layer 170 are linearly and analogically distributed. Using such characteristic of the solid electrolyte layer 170, the ion controllable transistor-based neuromorphic synaptic device 100 may linearly and analogically represent the synaptic weight by linearly and analogically updating the channel conductance by movement of ions present in the solid electrolyte layer 170 in response to a voltage pulse being applied to the gate area 160.

[0076] The aforementioned ion controllable transistor-based neuromorphic synaptic device 100 may secure a stable device characteristic and, at the same time, achieve a large-scale process and integration by using the solid electrolyte layer 170 that analogically updates the channel conductance and the synaptic weight by movement of ions in the solid electrolyte layer 170. A manufacturing method of the aforementioned ion controllable transistor-based neuromorphic synaptic device 100 may selectively use one of a gate-first process of forming the gate area 160 first and a gate-last process of forming the gate area 160 last. A gate-first manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 using the gate-first process is described with reference to FIG. 4 and FIGS. 5A to 5D, and a gate-last manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 using the gate-last process is described with reference to FIG. 6 and FIGS. 7A to 7D.

[0077] Also, the aforementioned ion controllable transistor-based neuromorphic synaptic device 100 may be implemented as a 3-terminal device that includes a terminal of the gate area 160, a terminal of the source area 130, and a terminal of the drain area 140. However, it is provided as an example only. Without being limited thereto, the ion controllable transistor-based neuromorphic synaptic device 100 may be implemented as a 4-terminal device that also includes a body terminal with the terminal of the gate area 160, the terminal of the source area 130, and the terminal of the drain area 140.

[0078] Also, a plurality of ion controllable transistor-based neuromorphic synaptic devices 100 may be provided to form a single synaptic array. Description related thereto is made with reference to FIG. 8.

[0079] FIG. 4 is a flowchart illustrating a gate-first manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment, and FIGS. 5A to 5D are X-Z cross-sectional views illustrating a gate-first manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment. Here, the ion controllable transistor-based neuromorphic synaptic device 100 manufactured through the following gate-first manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 may have the structure and the characteristics described above with reference to FIGS. 1 to 3, and an entity that performs the gate-first manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 may be a manufacturing system that is automated and mechanized.

[0080] Referring to FIG. 4 and FIGS. 5A to 5D, in operation S410, the manufacturing system may sequentially deposit the interlayer insulating film 150, the solid electrolyte layer 170, and the gate area 160 on the semiconductor substrate 110 as illustrated in FIG. 5A. In particular, the manufacturing system may form the solid electrolyte layer 170 using at least one of a sulfide-based material with a high ionic conductivity and present in a solid state [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, argyrodite, lithium phosphorus sulfide (LPS), LPS+LiC1], an oxide-based material [perovskite, NASICON (Na1+xZr2SixP3−xO12, 0<x<3), LISICON (Li2+2xZn1−xGeO4), LiPON (LixPOyNz), garnet], and an ion conductive polymer [polyethylene oxide (PEO), polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PTFE), nafion (C7HF13O5S.C2F4)], such that the manufactured ion controllable transistor-based neuromorphic synaptic device 100 may linearly and analogically update a channel conductance using a characteristic of the solid electrolyte layer 170 in which ions are linearly and analogically distributed.

[0081] Here, the channel area 120 may be formed in an upper area of the semiconductor substrate 100.

[0082] In operation S420, the manufacturing system may pattern a portion 510 of the interlayer insulating film 150, the solid electrolyte layer 170, and the gate area 160 provided on the channel area 120 that is formed on the semiconductor substrate 110 as illustrated in FIG. 5B. For example, by providing a photoresistance (PR) 511 on the portion 510 of the interlayer insulating film 150, the solid electrolyte layer 170, and the gate area 160 provided on the channel area 120, the manufacturing system may perform a patterning of leaving the portion 510 of the interlayer insulating film 150, the solid electrolyte layer 170, and the gate area 160 provided on the channel area 120.

[0083] The PR 511 used in operation S420 may be removed before operation S430.

[0084] In operation S430, the manufacturing system may form the source area 130 and the drain area 140 on portions 520 of the semiconductor substrate 110 exposed as a patterning result as illustrated in FIGS. 5B and 5C. Here, the portions 520 of the semiconductor substrate 110 are present at both sides of the channel area 120, respectively. For example, the manufacturing system may form the source area 130 and the drain area 140 on the portions 520 of the semiconductor substrate 110, respectively, exposed as the patterning result through one of an impurity ion implantation, a silicide alloy deposition including at least one of Al, W, Ti, Co, Ni, Er, and Pt, and a metal deposition including at least one of Au, Al, Ag, Mg, Ca, Yb, Cs—ITO, Ti, Cr, and Ni. Here, when the source area 130 and the drain area 140 are formed using the silicide alloy deposition or the metal deposition, one of an inkjet printing scheme, a printing process such as spraying, a chemical vapor deposition scheme, an evaporation scheme, and a sputtering scheme may be employed.

[0085] In operation S440, the manufacturing system may deposit the sacrificial insulating film 180 on the source area 130 and the drain area 140 as illustrated in FIG. 5D. Also, in operation S440, the manufacturing system may form a contact (not shown) through a back-end of line (BEOL).

[0086] FIG. 6 is a flowchart illustrating a gate-last manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment, and FIGS. 7A to 7D are X-Z cross-sectional views illustrating a gate-last manufacturing method of an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment. Here, the ion controllable transistor-based neuromorphic synaptic device 100 manufactured through the following gate-last manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 may have the structure and the characteristics described above with reference to FIGS. 1 to 3, and an entity that performs the gate-last manufacturing method of the ion controllable transistor-based neuromorphic synaptic device 100 may be a manufacturing system that is automated and mechanized.

[0087] Referring to FIG. 6 and FIGS. 7A to 7D, in operation S610, the manufacturing system may form the source area 130 and the drain area 140 on the semiconductor substrate 110 as illustrated in FIG. 7A. Here, the channel area 120 may be formed on the semiconductor substrate 110 and a dummy gate 190 may be provided on the channel area 120.

[0088] For example, the manufacturing system may form the source area 130 and the drain area 140 on areas provided at both sides of the channel area 120 on the semiconductor substrate 110, respectively, through one of an impurity ion implantation, a silicide alloy deposition including at least one of Al, W, Ti, Co, Ni, Er, and Pt, and a metal deposition including at least one of Au, Al, Ag, Mg, Ca, Yb, Cs—ITO, Ti, Cr, and Ni. Here, when the source area 130 and the drain area 140 are formed using the silicide alloy deposition or the metal deposition, one of an inkjet printing scheme, a printing process such as spraying, a chemical vapor deposition scheme, an evaporation scheme, and a sputtering scheme may be employed.

[0089] In operation S620, the manufacturing system may deposit the sacrificial insulating film 180 on the semiconductor substrate 110 as illustrated in FIG. 7B.

[0090] In operation S630, the manufacturing system may selectively remove the dummy gate 190 as illustrated in FIGS. 7B and 7C. For example, the manufacturing system may chemically polish and smoothen the sacrificial insulating film 180 until the dummy gate 190 is exposed and then may selectively remove only the dummy gate 190.

[0091] In operation S640, the manufacturing system may form the interlayer insulating film 150, the solid electrolyte layer 170, and the gate area 160 in a space 710 in which the dummy gate 190 is removed as illustrated in FIGS. 7C and 7D. In particular, the manufacturing system may form the solid electrolyte layer 170 using at least one of a sulfide-based material with a high ionic conductivity and present in a solid state [Li10GeP2S12, Li9.54Si1.74P1.44S11.7Cl0.3, argyrodite, lithium phosphorus sulfide (LPS), LPS+LiCl], an oxide-based material [perovskite, NASICON (Na1+xZr2SixP3−xO12, 0<x<3), LISICON (Li2+2xZn1−xGeO4), LiPON (LixPOyNz), garnet], and an ion conductive polymer [polyethylene oxide (PEO), polyethylene glycol (PEG), polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), nafion (C7HF13O5S.C2F4)], such that the manufactured ion controllable transistor-based neuromorphic synaptic device 100 may linearly and analogically update a channel conductance using a characteristic of the solid electrolyte layer 170 in which ions are linearly and analogically distributed.

[0092] Also, in operation 640, the manufacturing system may form a contact (not shown) through a back-end of line (BEOL).

[0093] FIG. 8 illustrates a synaptic array configured as an ion controllable transistor-based neuromorphic synaptic device according to an example embodiment.

[0094] Referring to FIG. 8, a synaptic array 800 may be implemented by providing a plurality of ion controllable transistor-based neuromorphic synaptic devices 100 described above with reference to FIGS. 1 to 3. Therefore, the synaptic array 800 may include the plurality of ion controllable transistor-based neuromorphic synaptic devices 100. As described above, each of the plurality of ion controllable transistor-based neuromorphic synaptic devices 100 may include the channel area 120 formed on the semiconductor substrate 110, the source area 130 and the drain area 140 formed at both sides of the channel area 120, respectively, the interlayer insulating film 150 formed on the channel area 120, the gate area 160 formed on the interlayer insulating film 150, and the solid electrolyte layer 170 inserted between the interlayer insulating film 150 and the gate area 160.

[0095] The synaptic array 800 has a structure in which a terminal of the gate area 160 and a terminal of the drain area 140 are separate in each of the plurality of ion controllable transistor-based neuromorphic synaptic devices 100 and thus, may support a parallel operation of updating a synaptic weight through the terminal of the gate area 160 and reading the synaptic weight through the terminal of the drain area 140.

[0096] While this disclosure includes specific example embodiments, it will be apparent to one of ordinary skill in the art that various alterations and modifications in form and details may be made in these example embodiments without departing from the spirit and scope of the claims and their equivalents. For example, suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.