Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

III-Nitride layers having spatially controlled regions or domains of porosities therein with tunable optical, electrical, and thermal properties are described herein. Also disclosed are methods for preparing and using such III-nitride layers.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.

A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.

A power device includes: a semiconductor layer, a well region, a body region, a gate, a source, a drain, a field oxide region, and a self-aligned drift region. The field oxide region is formed on an upper surface of the semiconductor layer, wherein the field oxide region is located between the gate and the drain. The field oxide region is formed by steps including a chemical mechanical polish (CMP) process step. The self-aligned drift region is formed in the semiconductor layer, wherein the self-aligned drift region is entirely located vertically below and in contact with the field oxide region.

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

A method for etching at least one layer of a gallium nitride (GaN)-based material is provided, the method including: providing the GaN-based layer having a front face; and at least one cycle including the following successive steps: modifying, by implanting hydrogen (H)- and/or helium (He)-based ions, at least some of a thickness of the GaN-based layer to form in the layer at least one modified portion extending from the front face, the implanting being carried out from a plasma, the modifying by implanting being carried out such that the modified portion extends from the front face and over a depth greater than 3 nm; oxidizing at least some of the modified portion by exposing the layer to an oxygen-based plasma, to define in the layer, at least one oxidized portion and at least one non-oxidized portion; and etching the oxidized portion selectively at the non-oxidized portion.

The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

A semiconductor body having a base carrier portion and a type III-nitride semiconductor portion is provided. The type III-nitride semiconductor portion includes a heterojunction and two-dimensional charge carrier gas. One or more ohmic contacts are formed in the type III-nitride semiconductor portion, the ohmic contacts forming an ohmic connection with the two-dimensional charge carrier gas. A gate structure is configured to control a conductive state of the two-dimensional charge carrier gas. Forming the one or more ohmic contacts comprises forming a structured laser-reflective mask on the upper surface of the type III-nitride semiconductor portion, implanting dopant atoms into the upper surface of the type III-nitride semiconductor portion, and performing a laser thermal anneal that activates the implanted dopant atoms.