PASSIVATION STACK ON A CRYSTALLINE SILICON SOLAR CELL

Abstract

A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N.sub.2O and SiH.sub.4 as precursor gasses in an N.sub.2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 2.

Claims

1. A method for manufacturing a passivation stack on a crystalline silicon solar cell device, the method comprising the steps of: providing a substrate comprising a crystalline silicon layer such as a crystalline silicon wafer or chip; cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer; depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride; and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride where the layer of silicon oxynitride is deposited at a temperature from 100° C. to 400° C., the step of depositing the layer of silicon oxynitride including: using N.sub.2O and SiH.sub.4 as precursor gasses; and depositing silicon oxynitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 2.

2. The method of claim 1, wherein the N.sub.2O and SiH.sub.4 precursor gasses are used in an N.sub.2 ambient atmosphere.

3. The method according to claim 1, wherein the N.sub.2O and SiH.sub.4 precursor gasses are used in an Ar ambient atmosphere.

4. The method according to claim 1, wherein the step of depositing the layer of silicon oxynitride includes using plasma-enhanced chemical vapour deposition.

5. The method according to claim 1, wherein the step of depositing the layer of silicon oxynitride includes depositing said layer with a thickness of less than 10 nm.

6. The method according to claim 1, wherein the step of depositing the capping layer of the hydrogenated dielectric material includes depositing said layer with a thickness of more than 25 nm.

7. The method according to claim 1, wherein the step of depositing the capping layer comprising the hydrogenated dielectric material includes depositing said hydrogenated dielectric capping layer in the same step as depositing the layer of silicon oxynitride.

8. The method according to claim 1, wherein the step of depositing the capping layer comprising the hydrogenated dielectric material includes depositing a layer of hydrogenated silicon nitride.

9. The method according to claim 1, wherein the step of depositing the capping layer comprising the hydrogenated dielectric material includes depositing the layer at the temperature of depositing the layer of silicon oxynitride.

10. The method according to claim 1, wherein, after the deposition of the layer of silicon oxynitride and the hydrogenated dielectric material capping layer further comprising heating the crystalline silicon substrate at a temperature of above 700° C.

11. The method of manufacturing a crystalline silicon solar cell according to claim 1.

12. A crystalline silicon solar cell device obtainable by the method according to claim 1.

13. A crystalline silicon solar cell comprising the solar cell device of claim 12.

14. The method according to claim 1, wherein the step of depositing the layer of silicon oxynitride includes depositing silicon oxyitride with a gas flow ratio of N.sub.2O to SiH.sub.4 below 1.

15. The method according to claim 1, wherein the step of depositing the layer of silicon oxynitride includes depositing silicon oxyitride with a gas flow ratio of N.sub.2O to SiH.sub.4 of approximately 0.5.

16. The method according to claim 1, wherein the step of depositing the silicon layer of oxynitride includes depositing said layer with a thickness of less than 5 nm.

17. The method according to claim 1, wherein the step of depositing the silicon layer of oxynitride includes depositing said layer with a thickness of 3 nm.

18. The method according to claim 1, wherein the step of depositing the capping layer of the hydrogenated dielectric includes depositing said layer with a thickness of 40 nm or more.

19. The method according to claim 1, wherein after the deposition of the layer of silicon oxynitride and the hydrogenated dielectric capping layer further comprising heating the crystalline silicon substrate at a temperature of approximately 800° C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In the following are described examples of preferred embodiments illustrated in the accompanying drawings, wherein:

[0036] FIG. 1 shows the effective minority carrier lifetime in various passivated crystal-line silicon substrates;

[0037] FIG. 2a shows the absorbance as a function of wavenumber in dielectric layers of different composition before high temperature treatment;

[0038] FIG. 2b shows the corresponding absorbance as a function of wavenumber in the same dielectric layers after high temperature treatment;

[0039] FIG. 3 shows the extinction coefficient as a function of wavelength for different dielectric layers;

[0040] FIG. 4 shows the effective minority carrier lifetime and the deposition rate of silicon oxynitride as a function of deposition temperature;

[0041] FIG. 5 shows the effective minority carrier lifetime as a function of the thickness of the silicon oxynitride layer; and

[0042] FIGS. 6a-6d show different embodiments f silicon solar cells according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0043] Silicon wafers used in the experiments were cleaned by a piranha etch and a subsequent removal of oxide in hydrofluoric acid. Both silicon oxynitride SiO.sub.XN.sub.Y and a capping layer of hydrogenated silicon nitride (SiN.sub.x for simplicity) were deposited by means of PEVCD, in the same PECVD chamber. In the experiments the SiO.sub.xN.sub.y layer was deposited with SiH.sub.4 and N.sub.2O as the precursors in N.sub.2 ambient. Alternatively, the SiO.sub.xN.sub.y layer may be deposited with SiH.sub.4 and N.sub.2O as the precursors in an Ar ambient atmosphere, or with no ambient atmosphere. The flow ratio of N.sub.2O to SiH.sub.4 was varied from 0:13 to 1000:13, resulting in different stoichiometric SiO.sub.xN.sub.y layers, ranging from hydrogenated amorphous silicon (a-Si) through SiO.sub.xN.sub.y to silicon oxide (SiO.sub.x). SiO.sub.xN.sub.y was deposited at temperatures ranging from 100° C. to 400° C. with a thickness from 1 to 40 nm and above. The temperature was measured in the deposition chamber as will be understood by a person skilled in the art. The capping layer of hydrogenated SiN.sub.x was deposited with SiH.sub.4 and NH.sub.3 as the precursor gasses.

[0044] The deposition temperature was varied from 130° C. to 400° C. and the flow ratio of SiH.sub.4 to NH.sub.3 was varied from 20:20 to 45:20, resulting SiN.sub.x layers with different reflective index. After depositing the SiN.sub.x/SiO.sub.xN.sub.y stack, some of the passivated samples were heated/annealed in a belt furnace with a peak temperature of 800° C. for 3 s, corresponding to a standard contact firing step during the manufacturing of crystalline silicon solar cells.

[0045] FIG. 1 shows the effective minority carrier lifetime, T.sub.eff in microseconds, for both p- and n-type crystalline silicon wafers passivated using a stack of SiN.sub.x/SiO.sub.xN.sub.y according to the present invention and compared with a standard passivation of a single layer of hydrogenated SiN.sub.x, both before firing, shown in open columns, and after firing, shown in hatched columns. In this experiment the SiO.sub.xN.sub.y layer was deposited with a N.sub.2O:SiH.sub.4 ratio of 20:45. The SiN.sub.x layer had a thickness of 75 nm. The p-type wafers were of Float-Zone (FZ) quality with a resistivity of 1-3 ohm.Math.cm, while the n-type wafers were of Czochralski (CZ) quality with a resistivity of 1-3 ohm.Math.cm. T.sub.eff was measured by means of Quasi steady-state photo conductance at an injection level of 10.sup.15 cm.sup.−3, as is also the case for the other effective minority carrier lifetime data disclosed herein. As can be seen from the figure, both the p- and n-type silicon material, with the SiN.sub.x/SiO.sub.xN.sub.y passivation, demonstrate minority carrier lifetimes in the millisecond range, both for as-deposited and after high temperature annealing, with an increased lifetime after annealing. The lifetime is significantly improved compared to the reference sample with only SiN.sub.x passivation. The minority carrier lifetime after annealing, for the samples passivated by SiN.sub.x/SiO.sub.xN.sub.y, was 2.3 millisecond and 3.2 milliseconds for the p- and n-type samples, respectively.

[0046] In FIGS. 2a and 2b absorbance, A, as a function of wavenumber, ω, is shown as measured by means of Fourier transform infrared spectroscopy (FTIR) of SiO.sub.xN.sub.y layers of different compositions, before and after firing, respectively. The results are compared to the absorbance in SiN.sub.x. The two dominating peaks, C and D, in the Figures are representative of Si—N(a-s) bonds at 835 cm.sup.−1 and Si—O(s) bonds at 1080 cm.sup.−1, respectively, as obtained by the extremes of SiN.sub.x at one side and a flow ratio of 1000:13 of N.sub.2O:SiH.sub.4 on the other side. The two intermediate curves shows the absorbance in layers deposited with N.sub.2O:SiH.sub.4 flow ratios of 20:45 and 20:13. The peak A at 470 cm.sup.−1 is indicative of Si—O(r) bonds, the peak B at 640 cm.sup.−1 indicates the presence of Si.sub.3—H(b) bonds, the peak E at 2300 cm.sup.−1 indicates Si.sub.3—H(s) bonds, while the peak F at 3400 cm.sup.−1 indicates N—H(s) bonds). Even if the stoichiometry varies with the different flow ratios the layers seem to be quite stable after the high temperature step, as seen when comparing FIGS. 2a and 2b. These results, in combination with the results from not shown capacitance-voltage measurements, indicate that the passivation is obtained mostly from chemical passivation of dangling bonds at the crystalline silicon surface.

[0047] The optical properties of the SiO.sub.xN.sub.y also vary with deposition conditions, as indicated in FIG. 3, where the extinction coefficient, K, as measured by means of ellipsometry, is shown as a function of wavelength, λ. In comparison, it is shown that SiO.sub.xN.sub.y has a significantly lower absorption than amorphous silicon in the spectral range up to 600 nanometers. In fact, the absorption of SiO.sub.xN.sub.y is comparable to that of low-refractive hydrogenated SiN.sub.x. Further, the best passivation results were obtained for SiO.sub.xN.sub.y layers with a relative high silicon portion, i.e. deposited with a low N.sub.2O:SiH.sub.4 ratio, in this example 20:45.

[0048] FIG. 4 shows the minority carrier lifetime, T.sub.eff in microseconds, of the previously mentioned p-type silicon as well as the deposition rate of SiO.sub.xN.sub.y as a function of deposition temperature ranging from 100° C. to 400° C. T.sub.eff is shown both for samples passivated by a SiN.sub.x/SiO.sub.xN.sub.y stack deposited with a N.sub.2O to SiH.sub.4 gas flow ratio of 20:13 and 20:45. The deposition rate shown corresponds to the flow ratio of 20:13. As seen from the figure, the minority carrier lifetime of the sample on which SiO.sub.xN.sub.y is deposited with the 20:13 gas flow ratio obtained a best T.sub.eff of 1 millisecond after firing, while the sample with SiO.sub.xN.sub.y deposited with a flow ratio was 20:45 obtained a best T.sub.eff of 2.3 milliseconds after firing. T.sub.eff for both samples approximately doubled when lowering the deposition temperature from 400° C. to 130° C. and 100° C., respectively. Another beneficial effect as seen from the figure, is that the deposition rate also increases with reduced temperature, which is a bit surprising, taking into account results from the prior art. For instance, keeping the flow ratio of N.sub.2O:SiH.sub.4 at 20:13, the deposition rate increases from 0.46 to 0.7 nm/s when the deposition temperature was decreased from 400° C. to 130° C.

[0049] In FIG. 5 the minority carrier lifetime, T.sub.eff, as a function of the thickness of the SiO.sub.xN.sub.y layer is shown under in an experiment performed under sub-optimal conditions. However, the results are believed to be valid also for SiO.sub.xN.sub.y layers deposited at the optimal conditions mentioned above. There is a peak in minority carrier lifetime at a SiO.sub.xN.sub.y layer thickness of 3 nm, while the lifetime for layers thicker than 10 nanometers is comparable to that at 10 nanometers.

[0050] Also, the deposition conditions of SiN.sub.x were shown to influence the passivation quality of the SiN.sub.x/SiO.sub.xN.sub.y stack. It was found that the passivation quality was improved with increasing deposition temperature of SiN.sub.x. The best minority carrier lifetime was obtained when the SiN.sub.x capping layer was deposited at 400° C., with the minority carrier lifetime shown to increase with the deposition temperature from 130° C. to 400° C., both before and after firing. The variation of flow ratio of SiH.sub.4:NH.sub.3 affects the optical properties of the SiN.sub.x layer, while the variation was found to have little influence on the minority carrier lifetime. It was found that in order to optimize the passivation, the SiN.sub.x as a capping layer should have a thickness of around 40 nm or above.

[0051] FIGS. 6a-6b show various examples of silicon solar cells provided with passivation stacks according to the present invention are shown. The functionality of such solar cells will be known to a person skilled in the art and will thus not be discussed in detail herein. The following figures are shown simplified and schematic, and the various features in the Figures are not drawn to scale. Identical reference numerals indicate identical or similar features in the figures.

[0052] In FIG. 6a, the reference numeral 1 indicates a silicon solar cell of a type that is usually referred to as a standard silicon solar cell. A crystalline silicon wafer 2 is passivated by means of a first layer 3 of SiO.sub.xN.sub.y capped by a second layer 5 of a hydrogenated dielectric, here shown in the form of hydrogenated SiN.sub.x. In sum the first and second layers 3, 5 act as a combined passivation and anti-reflection coating on a front surface 21 of the solar cell 1. A thin, highly doped region 25 is provided at the front surface 21 so as to constitute a p-n junction/diode together with the base doping of the silicon wafer 2. A set of front side contacts 7 is provided on top of the first layer 3 on the front side 21 of the solar cell 1, while a set of back side contacts 9 have been provided at a backside 23, contacting a highly doped backside region 27. The front side contacts are shown prior to firing, i.e. prior to establishing contact with the highly doped surface region 25.

[0053] FIG. 6b shows a so-called bifacial solar cell 1 where the passivation/anti-reflection stack constituted by the first layer 3 of SiO.sub.xN.sub.y and the second layer 5 of SiN.sub.x is provided on both sides of the solar cell 1. In alternative embodiments the two layers 3, 5 of the passivation stack SiN.sub.x/SiO.sub.xN.sub.y may be provided only on the front surface side 21 or on the backside 23.

[0054] In FIG. 6c, the two layers 3, 5 of the passivation stack SiN.sub.x/SiO.sub.xN.sub.y are shown as provided on both sides of a passivated emitter rear contact (PERC) solar cell, while in FIG. 6d the two layers 3, 5 are shown used on both sides of a back-contacted back junction solar cell. In the latter case, both polarity contacts 7, 9 are provided on the backside 23 of the solar cell, usually in an interdigitated finger pattern following the shape of oppositely doped emitter and base regions 29, 29′. Also in these embodiments the two layers 3, 5 of the passivation stack SiN.sub.x/SiO.sub.xN.sub.y may be provided only on the front side 21 or on the backside 23.