NETWORK NODE, CONTROL MODULE FOR A COMPONENT AND ETHERNET RING

Abstract

The invention relates to network nodes comprising: a first computing unit (CPU.sub.a); at least one second computing unit (CPU.sub.b); an internal switch (Sw.sub.i); and an external switch (Sw.sub.e), wherein the internal switch (Sw.sub.i) is connected to the first computing Nunit (CPU.sub.a), the at least second computing unit (CPU.sub.b) and to the external switch (Sw.sub.e) and wherein the external switch (Sw.sub.e) has at least one port for data originating from other network nodes. The invention also relates to a control module and an Ethernet ring.

Claims

1. A network node comprising: a first computing unit and at least one second computing unit; and an internal switch and an external switch, the internal switch being connected to the first computing unit, the at least second computing unit, and the external switch, the external switch having at least one port for data that comes from other network nodes.

2. The network node of claim 1, further comprising at least one interface for outputting control commands to an assembly.

3. The network node of claim 2, wherein the at least one interface comprises a port of the external switch.

4. The network node of claim 1, wherein the internal switch is configured such that data from at least one computing unit of the first computing unit and the at least one second computing unit is transferred to the internal switch via at least one port of the switch and is transferred to the external switch via at least one other port of the internal switch.

5. The network node of claim 1, wherein the external switch comprises at least one port for communicating with a respective node.

6. The network node of claim 1, wherein the first computing unit and the at least second computing unit carry out computing operations, and the network node switches off when results of the computing operations differ.

7. The network node of claim 1, wherein at least one port on the internal switch is configured, at a connection that connects the internal switch to the external switch, such that packets that are identified with an attribute that is reserved for packets transporting data from the first computing unit to the second computing unit are not forwarded from the port on the internal switch to the external switch.

8. The network node of claim 1, wherein at least one port on the external switch is configured, at a connection that connects the internal switch to the external switch, such that packets that are identified with an attribute that is reserved for packets transporting data from the first computing unit to the second computing unit are rejected by the external switch.

9. The network node of claim 1, wherein at least one port on the external switch is configured such that a data rate that is forwarded to the internal switch is limited to a predefined data rate.

10. The network node of claim 1, wherein at least one port on the internal switch is configured such that data packets from a port on the external switch are rejected when a predefined data rate is exceeded.

11. The network node of claim 9, wherein the predefined data rate depends on an available computing time and a buffer size such that data interchange between the first computing unit and the second computing unit is not impaired.

12. A control module for at least one component, the control module comprising: at least one first node and at least one second node, each node of the at least one first node and the at least one second node comprising: a first computing unit and at least one second computing unit; and an internal switch and an external switch, the internal switch being connected to the first computing unit, the at least second computing unit, and the external switch, the external switch having at least one port for data that comes from other network nodes; and an interface for outputting control data and for receiving data relating to a component to be controlled, in which, when a node switches off, another node undertakes the tasks of the node.

13. An Ethernet ring comprising: at least two nodes that form a control module, each node of the at least two nodes comprising: a first computing unit and at least one second computing unit; and an internal switch and an external switch, the internal switch being connected to the first computing unit, the at least second computing unit, and the external switch, the external switch having at least one port for data that comes from other network nodes, a component that is connected to the control module and is to be controlled by the control module.

14. The Ethernet ring of claim 13, wherein the at least two nodes comprise three nodes that form the control module, two nodes of the three nodes having an interface for communicating with the component.

15. The Ethernet ring of claim 13, wherein the respective node further comprises at least one interface for outputting control commands to an assembly.

16. The Ethernet ring of claim 15, wherein the at least one interface comprises a port of the respective external switch.

17. The Ethernet ring of claim 13, wherein the respective internal switch is configured such that data from at least one computing unit of the first computing unit and the at least one second computing unit of the respective node is transferred to the respective internal switch via at least one port of the switch and is transferred to the respective external switch via at least one other port of the respective internal switch.

18. The Ethernet ring of claim 1, wherein the respective external switch comprises at least one port for communicating with a respective node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG. 1 shows a configuration of a control module according to the prior art; and

[0012] FIG. 2 shows an exemplary embodiment of a control module.

DETAILED DESCRIPTION

[0013] FIG. 1 depicts one embodiment of a control module STM having a plurality of network nodes (e.g., the network nodes or nodes 1, K1, nodes 2, K2 and nodes 3, K3). Each of the nodes K1, K2, K3 is in the form of a duplex control computer (DCC). In other words, the node K1, for example, has a first central computing unit (CPU) CPU.sub.a having an associated switch Sw.sub.a and a second central computing unit CPU.sub.b and an associated switch Sw.sub.b. The two other nodes illustrated, the second node K2 and the third node K3, are configured accordingly. The control module STM also has at least one interface IF for making it possible to communicate with at least one component or assembly to be controlled.

[0014] The control module STM including the three nodes K1, K2 and K3 is intended to be “fail operational.” In other words, in the event of the defective function of at least one computing unit in one of the nodes, another node is intended to be able to undertake this task. If, for example, the computing unit CPU.sub.a in the node K1 fails or operates defectively, one of the two other nodes K2 or K3 is intended to be able to undertake this task.

[0015] The determination regarding whether a node is operating defectively is made as stated below: the aim is for the control module STM to output a correct control command for an assembly (e.g., a sensor or an actuator) via the interface IF.

[0016] For this purpose, the first computing unit CPU.sub.a and the second computing unit CPU.sub.b in the node that is primarily assigned this task calculate the necessary operations. A separate calculation is therefore carried out. The data that has been calculated in the first computing unit CPU.sub.a is transmitted to a switch Sw.sub.a assigned to this computing unit (e.g., transferred to the switch Sw.sub.a via a first port P1).

[0017] The second computing unit CPU.sub.b in the node K1 likewise calculates the data required for the respective control command and passes the data to the associated second switch Sw.sub.b via the port P1 of the switch. The data may be interchanged between the two computing units CPU.sub.a and CPU.sub.b and may be consolidated via a further port P2 on the switch Sw.sub.b assigned to the second computing unit CPU.sub.b and on the switch Sw.sub.a assigned to the first computing unit CPU.sub.a. If it is now determined that the results differ from one another, at least one of the two computing units CPU.sub.a or CPU.sub.b or one of the two switches Sw.sub.a or Sw.sub.b has not operated correctly. In order to exclude a malfunction, the entire first node K1 is therefore switched off, and one of the two other nodes (e.g., the second node K2 or the third node K3) undertakes the tasks of the first node K1. The first node K1 therefore operates according to the “fail silent” principle (e.g., this node independently switches off as soon as an incorrect method of operation is suspected).

[0018] FIG. 2 schematically illustrates an exemplary configuration of the in which the control module STM for an assembly has three nodes, a first node K1, a second node K2 and a third node K3. Alternatively, a different number of nodes≧2 may be provided.

[0019] The assembly may be a sensor, an actuator, or a combination of the two. Some examples of sensors and actuators are cited below in a non-conclusive manner. Examples of sensors are steering angle sensors, wheel speed sensors, acceleration sensors, or complex radar-based, lidar-based, camera-based, or ultrasound-based environmental sensors in vehicles, train proximity sensors at the railroad crossing, or pressure, temperature, and flow sensors in industrial installations. Actuators in the vehicle are, for example, steering angle actuators, brake force actuators, or drive motors. In industrial installations, actuators may be formed by valves, drives, pumps, and, at a railroad crossing, by the barriers.

[0020] For a control command that is transmitted to an assembly via an interface IF, the calculation is again carried out using the first computing unit CPU.sub.a and the second computing unit CPU.sub.b. These computing units CPU.sub.a and CPU.sub.b forward the determined result to an internal switch Sw.sub.i. In the implementation shown in FIG. 2, the CPU.sub.a is connected to the internal switch Sw.sub.i via a first port P1.sub.i, and the CPU.sub.b is connected via a second port P2.sub.i. A connection between the internal switch Sw.sub.i and an external switch Sw.sub.e may be established via a third port P3.sub.i.

[0021] A port may be in the form of an input/output, for example. A port may be, for example, an interface of a network component, such as a switch that may be addressed via a port address, for example. Alternatively, a port may only be in the form of an input or an output.

[0022] Only packets that are directed from one computing unit to the respective other computing unit inside a node, the “X-lane traffic”, or else packets that come from the first node K1 (e.g., the latter is the data source) or are directed to the first node as the destination (e.g., the first node is the data sink) pass via the internal switch Sw.sub.i.

[0023] In the first case, this is carried out solely via the first port P1.sub.i and the second port P2.sub.i. In the second case, the data packets are forwarded from the external switch Sw.sub.e to the internal switch Sw.sub.i and from the internal switch Sw.sub.i to the external switch Sw.sub.e via the port P3.sub.i.

[0024] Data packets that are only forwarded do not reach the internal switch Sw.sub.i.

[0025] If a difference is now determined, the relevant node, in which a difference in the results from the two computing units inside the node has been detected, switches off again.

[0026] For this reason, an attempt is made to avoid data packets that come from the outside being able to interfere with the communication between the computing unit CPU.sub.a and the computing unit CPU.sub.b. If this were to happen, for example, because a defective node or a defective assembly sends a large volume of data with incorrect header attributes, this one defective node may result in a plurality of duplex control computers DCC switching off. A fail operational behavior would then no longer exist in this case.

[0027] Data packets that are forwarded only from one node run via the external switch Sw.sub.e. The external switch Sw.sub.e has ports or inputs/outputs in order to make it possible to communicate with further nodes in the network. Optionally, the node has an interface IF in order to make it possible to communicate with at least one assembly. This interface IF may be implemented, for example, via a port of the external switch Sw.sub.e.

[0028] The advantages of the proposed architecture lie in the following points. If a data packet is forwarded from one node to the other node (e.g., from the first node K1 to the third node K3), two transmissions or hops are to take place inside each node (e.g., from the switch Sw.sub.a assigned to the first computing unit to the switch Sw.sub.b assigned to the second computing unit) before the data packet is forwarded to the next node. This enhancement has negative effects on the failure probability because an error may occur during each transmission and on a time delay that occurs during the transmission. If the assembly to be controlled is also equipped with a duplex control computer DCC, this disadvantage is multiplied by the number of assemblies since two transmissions or hops also respectively take place in the duplex control computer DCC of the assembly.

[0029] In the configuration shown in FIG. 2, the two switches Sw.sub.a,b are each assigned to a computing unit CPU.sub.a,b. This makes it possible to construct a node from two identical “lane modules” each including, inter alia, a computing unit and a switch. Different paths for the data to be calculated through the node, through two computing units in the configuration shown, are provided, for example, in a “lane module” or “path module.” An embodiment having identical lane modules is advantageous, for example, in the case of smaller quantities since the development costs for a node may be kept low since only one lane module is to be developed.

[0030] In another configuration, the switch Sw.sub.a assigned to the computing unit CPU.sub.a and the switch Sw.sub.b assigned to the computing unit CPU.sub.b are functionally in the form of a switch that is assigned to both computing units. In this case, the port P2.sub.i would be dispensed with or would be replaced with an internal connection in the switch. For larger quantities, the implementation with only one switch would be advantageous. Lower unit costs would offset the higher development costs for the more complicated circuit board and the more complex switch equipped with more ports.

[0031] In contrast, in another configuration, data packets that do not come from a data node and are not directed to the latter as the destination are forwarded only via the external switch Sw.sub.e. This results in only one hop for forwarded data packets occurring inside a node.

[0032] In addition to the advantage described above in the alternative implementation having a single switch, this also has the advantage that there is no need to use a complex switch that is possibly not available in a suitable embodiment as a mass product.

[0033] Another advantage is that largely commercially available switches may be used since no port prioritization is required. As a result, it is possible to use switches that are available on the market (e.g., switches that are not specifically designed for the application). This has a positive influence on the availability and the price. Switches that may currently be used in the automotive sector and in which aspects such as a wide operating temperature range, current consumption, and also price play a role are also available only with a relatively small number of ports. Another aspect is that few of these switches provide support for time-sensitive networks TSN, as specified in IEEE 802.1Qbu or IEEE 802.1Qbv, for example (e.g., support for time-sensitive networks in which long, low-priority data packets may be interrupted for high-priority short data packets).

[0034] The problem of port prioritization is to be explained in connection with FIG. 1. If, for example, the third node K3 is operating defectively and sends a plurality of defective packets to the first node K1, the first node K1 does not have any possible way of giving preference to data packets that internally come from the two respective computing units and are compared over the external data packets from the node 3 if the defective packets from K3 have the same prioritization information in the header. In order to switch off this error source, both nodes are to support port-based prioritization or port prioritization (e.g., must prioritize the packets depending on the port at which the packets were received).

[0035] In contrast, this is not required in the structure shown in FIG. 2. Since the X-lane data or X-lane traffic (e.g., data that is interchanged between the two computing units inside a node) is communicated only via the internal switch Sw.sub.i, an Ethertype, a VLAN ID, and/or a VLAN priority may be used for this data.

[0036] The ports that connect the internal switch Sw.sub.i to the external switch Sw.sub.e may be configured such that X-lane data is not forwarded. Therefore, no data packets are interchanged between the internal switch Sw.sub.i and the external switch Sw.sub.e if the data packets have a corresponding attribute that is reserved for data packets that are directed from one computing unit in the node to the other computing unit. The attributes are, for example, header attributes in the data header or “header” (e.g., “VLAN tags” or “Ethertypes”). It is also possible to provide a plurality of connections between the internal switch Sw.sub.i and the external switch Sw.sub.e. In order to prevent data from being interchanged, at least either the corresponding internal switch Sw.sub.i does not forward a data packet directed from one computing unit to the other or the corresponding external switch Sw.sub.e rejects this packet at each connection. In order to increase the reliability, provision may also be made for both the internal switch Sw.sub.i and the external switch Sw.sub.e to be configured accordingly.

[0037] In addition, the data traffic entering the switch Sw.sub.i from the outside may be limited using simple standard measures. It is therefore possible to provide that, as a result of an external error, so many defective data packets never arrive at a computing unit CPU.sub.a,b that the X-lane data may no longer be processed on account of resource bottlenecks (e.g., buffer size or computing time). The X-lane traffic may therefore be reliably prioritized above all other data classes or traffic classes without one of the switches having to support port-based prioritization. For this purpose, the external switch Sw.sub.e may be configured such that data packets are forwarded to the internal switch Sw.sub.i only until a predefined data rate is reached. Alternatively or additionally, the internal switch Sw.sub.i may be configured such that the internal switch Sw.sub.i rejects packets coming from the external switch Sw.sub.e if the predefined data rate is exceeded. The predefined data rate is such that the data traffic between the CPUs is not impaired or is not significantly impaired, which depends, inter alia, on the available computing power and the size of the data buffers in the switch or/and the computing unit. There is only insignificant impairment if the data may still be interchanged in a predefined bandwidth and within a predefined delay.

[0038] In the case of a plurality of connections between the internal switch Sw.sub.i and the external switch Sw.sub.e, at least one switch is advantageously configured for each connection such that the data traffic may be limited.

[0039] This makes it possible to use commercially available switches that are, for example, cost-effective in comparison with field programmable gate arrays (FPGAs). In the architecture according to FIG. 1, prioritization by identifications, tags, or other identifiers adhering to the data frame would not be sufficient since it cannot be excluded that a defectively operating node (e.g., the node K3) generates data frames with this tag.

[0040] In the architecture according to FIG. 2, data frames with these tags would be rejected both at the transmitting port and at the receiving port of the line or link connecting the internal switch Sw.sub.i and the external switch Sw.sub.e, with the result that the data frames may not interfere with the X-lane traffic. Data that is to be received from the outside may be limited in terms of bandwidth on the same link, with the result that the data is not able to interfere with the X-lane traffic as a result of the receiving buffers or the CPU being overloaded.

[0041] Alternatively, a number of greater than or equal to two computing units may be provided inside a node. The computing units may communicate via one or more internal switches Sw.sub.i. The probability of a node being switched off may therefore be reduced, for example, if a majority decision is made (e.g., a computing result is recognized as correct as soon as at least two nodes have the same result).

[0042] A plurality of interfaces IF may be provided in order to communicate with an assembly in different ways or/and with a plurality of assemblies.

[0043] An Ethernet ring may be formed, for example, by a control module having two or more nodes. In this case, an interface to the respective assembly may be provided in one or more nodes. Communication with different assemblies may take place via different interfaces or the same interfaces.

[0044] The elements and features recited in the appended claims may be combined in different ways to produce new claims that likewise fall within the scope of the present invention. Thus, whereas the dependent claims appended below depend from only a single independent or dependent claim, it is to be understood that these dependent claims may, alternatively, be made to depend in the alternative from any preceding or following claim, whether independent or dependent. Such new combinations are to be understood as forming a part of the present specification.

[0045] While the present invention has been described above by reference to various embodiments, it should be understood that many changes and modifications can be made to the described embodiments. It is therefore intended that the foregoing description be regarded as illustrative rather than limiting, and that it be understood that all equivalents and/or combinations of embodiments are intended to be included in this description.