METHOD AND APPARATUS FOR SUPPORTING LOW BIT RATE CODING, AND COMPUTER STORAGE MEDIUM

Abstract

The disclosure discloses a method for supporting low bit rate coding. A source data packet to be coded is repeated for i times, and the data packet which is repeated for i times is coded. The disclosure also discloses an apparatus for supporting low bit rate coding and a computer storage medium.

Claims

1. An apparatus for supporting low bit rate coding, at least comprising: a repeater and a coder, wherein the repeater is configured to repeat a source data packet to be coded for i times, i being a positive integer; and the coder is configured to code the data packet repeated by the repeater, coding being Low Density Parity Check (LDPC) coding, Turbo coding or convolutional coding.

2. The apparatus according to claim 1, wherein the repeater is configured to directly repeat the source data packet to be coded for i times, or the source data packet comprises j sub-data packets, the j sub-data packets are repeated for i times respectively, j is a positive integer, and i is 1, 2, 3, 4, 5 or 6 specifically.

3-18. (canceled)

19. A method for supporting low bit rate coding, at least comprising: repeating a source data packet to be coded for i times, and coding the data packet repeated for i times, i being a positive integer, wherein coding is Low Density Parity Check (LDPC) coding, Turbo coding or convolutional coding.

20. The method according to claim 19, wherein repeating a source data packet to be coded for i times comprises directly repeating the source data packet to be coded for i times, or the source data packet comprises j sub-data packets, the j sub-data packets are repeated for i times respectively, j is a positive integer, and i is 1, 2, 3, 4, 5 or 6 specifically.

21. The method according to claim 20, wherein the coding is (nb×z, kb×z) LDPC coding, and a master code data packet is obtained by coding, where nb is a column number of a basic parity check matrix, z is an expansion factor, z, nb and kb are positive integers, kb=nb-mb, mb is a row number of the basic parity check matrix, and mb is a positive integer.

22. The method according to claim 21, further comprising: reading, before coding, the basic parity check matrix, wherein coding comprises: setting values of r non −1 element in the basic parity check matrix as −1, where r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

23. The method according to claim 22, further comprising: carrying out rate matching on the master code data packet so as to obtain an N-bit coded data packet, N being a code length.

24. The method according to claim 22, wherein the basic parity check matrix is as follows specifically: TABLE-US-00015 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0 wherein the leftmost column represents row indexes, the uppermost row represents column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix.

25. The method according to claim 19, further comprising: filling, before repeating the source data packet to be coded for i times, the source data packet to be coded with q1 elements so as to expand the source data packet to be coded into a first data packet, q1 being a positive integer.

26. The method according to claim 19, further comprising: filling, after repeating the source data packet to be coded for i times, the data packet repeated for i times with q2 elements so as to obtain a second data packet, q2 being a positive integer.

27. The method according to claim 26, wherein the coding is (nb×z, kb×z) LDPC coding, the basic parity check matrix is read before coding, values of r non −1 element in the basic parity check matrix are set as −1, and then coding is carried out to obtain a check data packet, where nb is a column number of the basic parity check matrix, z is an expansion factor, z, nb and kb are positive integers, kb=nb−mb, mb is a row number of the basic parity check matrix, mb is a positive integer, r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

28. The method according to claim 27, wherein the basic parity check matrix is as follows specifically: TABLE-US-00016 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0 wherein the leftmost column represents row indexes, the uppermost row represents column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix.

29. The method according to claim 28, further comprising: combining the coded check data packet and the source data packet into a master code data packet.

30. The method according to claim 29, further comprising: carrying out rate matching on the master code data packet so as to obtain an N-bit coded data packet, N being a code length.

31. The method according to claim 23, wherein the coding is (16×42, 8×42) LDPC coding, the basic parity check matrix is an 8×16 matrix, an expansion factor z=42, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.71] (k=72 bits), when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=1024 bits), the signalling sequence a is repeated for one time and expanded to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=a.sub.i-180 i=180,181, . . . ,209
d.sub.i=a.sub.i-122 i=222,223, . . . ,293
d.sub.i=a.sub.i-264 i=294,295, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 408-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.407]; and finally, a 1024-bit coded data packet e is constructed by the master code data packet s, e being:
e.sub.j=s.sub.j j=0,1, . . . ,407
e.sub.j=s.sub.j-408 j=408,409, . . . ,815
e.sub.j=s.sub.j-816 j=816,817, . . . ,1023.

32. The method according to claim 23, wherein the coding is (16×42, 8×42) LDPC coding, the basic parity check matrix is an 8×16 matrix, an expansion factor z=42, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), the signalling sequence a is repeated for one time and expanded to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=a.sub.i-172 i=172,173, . . . ,209
d.sub.i=a.sub.i-214 i=214,215, . . . ,293
d.sub.i=a.sub.i-256 i=294,295, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:
e.sub.j=s.sub.j j=0,1, . . . ,415
e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

33. The method according to claim 23, wherein the coding is (16×42, 8×42) LDPC coding, the basic parity check matrix is an 8×16 matrix, an expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39](k=40 bits), when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), the signalling sequence f is repeated for one time and expanded to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=f.sub.i-254 i=254,255, . . . ,293
d.sub.i=f.sub.i-296 i=296,297, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335,], and the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:
h.sub.j=g.sub.j i=0,1, . . . ,375
h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

34. The method according to claim 30, wherein the coding is (16×42, 8×42) LDPC coding, the basic parity check matrix is an 8×16 matrix, an expansion factor z=42, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), there are two processing modes: in a first mode, firstly, the signalling sequence a is repeated for one time and expanded to obtain a 168-bit data packet; then, the data packet is filled with 168 bit elements and expanded to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=a.sub.i-172 i=172,173, . . . ,209
d.sub.i=a.sub.i-214 i=214,215, . . . ,293
d.sub.i=a.sub.i-256 i=294,295, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:
e.sub.j=s.sub.j j=0,1, . . . ,415
e.sub.j=s.sub.j-416 j=416,417, . . . ,671; in a second mode, firstly, the signalling sequence a is filled with 4 bit elements to expand into a first 84-bit data packet, the first data packet is split into two 42-bit sub-data packets, and then each sub-data packet is repeated for one time respectively; then, the repeated data packet is filled with 168 bit elements and expanded to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=a.sub.i-172 i=172,173, . . . ,209
d.sub.i=a.sub.i-214 i=214,215, . . . ,293
d.sub.i=a.sub.i-256 i=294,295, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:
e.sub.j=s.sub.j j=0,1, . . . ,415
e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

35. The method according to claim 30, wherein the coding is (16×42, 8×42) LDPC coding, the basic parity check matrix is an 8×16 matrix, an expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39](k=40 bits), and when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), there are two processing modes: in a first mode, firstly, the signalling sequence f is repeated for one time and expanded into a 84-bit data packet, and the data packet is filled with 252 bit elements to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=f.sub.i-254 i=254,255, . . . ,293
d.sub.i=f.sub.i-296 i=296,297, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:
h.sub.j=g.sub.j i=0,1, . . . ,375
h.sub.j=g.sub.j-376 i=376,417, . . . ,671; in a second mode, firstly, the signalling sequence f is filled with 2 bit elements to expand into a first 42-bit data packet, and the first data packet is repeated for one time; then, the repeated data packet is filled with 252 bit elements to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:
d.sub.i=f.sub.i-254 i=254,255, . . . ,293
d.sub.i=f.sub.i-296 i=296,297, . . . ,335;
d.sub.i=0 i=others then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:
h.sub.j=g.sub.j i=0,1, . . . ,375
h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

36. A computer storage medium, wherein a computer program is stored therein and is configured to execute a method for supporting low bit rate coding, the method at least comprises the following steps of: repeating a source data packet to be coded for i times, and coding the data packet repeated for i times, i being a positive integer, wherein coding is Low Density Parity Check (LDPC) coding, Turbo coding or convolutional coding.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIG. 1 is a structural diagram of an apparatus for supporting low bit rate coding provided by a first embodiment of the disclosure;

[0029] FIG. 2 is a structural diagram of an apparatus for supporting low bit rate coding provided by a second embodiment of the disclosure; and

[0030] FIG. 3 is a flowchart of a method for supporting low bit rate coding provided by a third embodiment of the disclosure.

DETAILED DESCRIPTION

[0031] The basic idea of the disclosure is that: a source data packet to be coded is repeated for i times, and the data packet which is repeated for i times is coded. Thus, low bit rate coding can be achieved, and coding gains can be fully utilized.

[0032] The disclosure is further illustrated below with reference to the drawings and specific embodiments in detail.

First Embodiment

[0033] The embodiment of the disclosure implements an apparatus for supporting low bit rate coding. As shown in FIG. 1, the apparatus at least includes: a repeater 102 and a coder 104, wherein

[0034] the repeater 102 is configured to repeat a k-bit source data packet x to be coded for i times, i being a positive integer; and

[0035] the coder 104 is configured to code the data packet repeated by the repeater 102, coding being LDPC coding, Turbo coding or convolutional coding.

[0036] The repeater 102 is specifically configured to directly repeat the source data packet x to be coded for i times, or the source data packet x includes j sub-data packets, the j sub-data packets are repeated for i times respectively, j is a positive integer, and i may be 1, 2, 3, 4, 5 or 6 generally.

[0037] Specifically, the coder 104 is an (nb×z, kb×z) LDPC coder, and a master code data packet C′ is obtained by coding, where nb is a column number of a basic parity check matrix, z is an expansion factor, z, nb and kb are positive integers, kb=nb−mb, mb is a row number of the basic parity check matrix, and mb is a positive integer. Before the coder 104 carries out coding, the basic parity check matrix is read, and then values of r non −1 element in the basic parity check matrix are set as −1, where r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

[0038] The apparatus may further include a rate matcher 106, configured to carry out rate matching on the master code data packet C′ so as to obtain an N-bit coded data packet, N being a code length.

[0039] The working process of the apparatus for supporting low bit rate LDPC code coding according to the present embodiment is illustrated below by means of four specific examples.

First Example

[0040] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00001 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 23 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 36 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 18 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0041] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.71] (k=72 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=1024 bits), the repeater 102 repeats the signalling sequence a for one time, and then expands to obtain a 336-bit data packet d=[(d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=a.sub.i-180 i=180,181, . . . ,209

d.sub.i=a.sub.i-222 i=222,223, . . . ,293

d.sub.i=a.sub.i-264 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0042] the coder 104 carries out LDPC coding on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and combines the signalling sequence a and the 336-bit check data packet b into a 408-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.407]; and

[0043] the rate matcher 106 constructs a 1024-bit coded data packet e by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,407

e.sub.j=s.sub.j-408 j=408,409, . . . ,815

e.sub.j=s.sub.j-816 j=816,817, . . . ,1023.

Second Example

[0044] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00002 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 23 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 36 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 18 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0045] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), the repeater 102 repeats the signalling sequence a for one time, and then expands to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0046] the coder 104 carries out LDPC coding on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and combines the signalling sequence a and the 336-bit check data packet b into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0047] the rate matcher 106 constructs a 672-bit coded data packet e by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Third Example

[0048] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00003 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 39 −1 13 −1 22 −1 9 20 −1 −1 −1 −1 −1 −1 −1 1 17 −1 −1 26 −1 2 −1 18 40 4 −1 −1 −1 −1 −1 −1 2 34 −1 24 −1 28 −1 19 −1 −1 8 29 −1 −1 −1 −1 −1 3 −1 36 6 −1 14 −1 38 −1 −1 −1 16 30 −1 −1 −1 −1 4 −1 33 −1 39 −1 24 −1 27 18 −1 −1 18 33 −1 −1 −1 5 9 −1 30 −1 −1 4 −1 36 −1 12 −1 −1 24 0 −1 −1 6 26 −1 12 −1 0 −1 15 −1 −1 −1 32 −1 −1 −1 0 −1 7 −1 30 −1 10 28 −1 34 −1 −1 −1 −1 11 −1 −1 −1 0

[0049] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, the basic parity check matrix is an 8×16 matrix, the expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39] (k=40 bits), and when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), the repeater 102 repeats the signalling sequence f for one time, and then expands to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i=0 i=others

[0050] the coder 104 carries out LDPC coding on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and combines the signalling sequence a and the 336-bit check data packet b into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and

[0051] the rate matcher 106 constructs a 672-bit coded data packet h by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671

Fourth Example

[0052] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0053] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), the repeater 102 repeats the signalling sequence a for one time, and then expands to obtain a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0054] the coder 104 modifies an element ‘0’ in the second row and the sixth column in the basic parity check matrix into ‘−1’ first. The modified basic parity check matrix is as follows:

TABLE-US-00005 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 −1 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0055] the coder 104 carries out LDPC coding on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and combines the signalling sequence a and the 336-bit check data packet b into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0056] the rate matcher 106 constructs a 672-bit coded data packet e by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Second Embodiment

[0057] The embodiment of the disclosure implements an apparatus for supporting low bit rate coding. As shown in FIG. 2, the apparatus at least includes: a repeater 102 and a coder 104, wherein

[0058] the repeater 102 is configured to repeat a k-bit source data packet x to be coded for i times, i being a positive integer; and

[0059] the coder 104 is configured to code the data packet repeated by the repeater 102, coding being LDPC coding, Turbo coding or convolutional coding.

[0060] Specifically, the coder 104 is an (nb×z, kb×z) LDPC coder, and a check data packet P is obtained by coding, where nb is a column number of a basic parity check matrix, (nb−kb) is a row number of the basic parity check matrix, z is an expansion factor, and z, nb and kb are positive integers. Before the coder 104 carries out coding, the basic parity check matrix is read, and then values of r non −1 element in the basic parity check matrix are set as −1, where r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

[0061] The apparatus may further include a master code generator 105, the master code generator 105 combines the check data packet P, obtained by the coder 104, and the source data packet x into a master code data packet C′, and an N-bit coded data packet can be obtained by carrying out rate matching on the master code data packet C′ via a rate matcher 106, N being a code length.

[0062] The apparatus may further include a first-class filler 101, configured to fill the source data packet x to be coded with q1 elements so as to obtain a first data packet x.sub.0 by expansion, q1 being a positive integer.

[0063] The repeater 102 directly repeats the first data packet x.sub.0 for i times, or the first data packet x.sub.0 is split into j sub-data packets, the j sub-data packets are repeated for i times respectively, j is a positive integer, and i may be 1, 2, 3, 4, 5 or 6 generally.

[0064] The apparatus can fill the data packet repeated by the repeater 102 with q2 elements via a second-class filler 103 so as to obtain a second data packet Y, q2 being a positive integer.

[0065] The apparatus may further include the rate matcher 106, configured to carry out rate matching on the master code data packet C so as to obtain the N-bit coded data packet, N being a code length.

[0066] The working process of the apparatus for supporting low bit rate LDPC code coding according to the present embodiment is illustrated below by means of two specific examples.

First Example

[0067] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00006 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 23 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 36 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 18 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0068] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), there are two processing modes.

[0069] In the first mode, when there is not a first-class filler 101,

[0070] the repeater 102 repeats the signalling sequence a for one time, and then expands to obtain a 168-bit data packet;

[0071] the second-class filler 103 fills the data packet repeated by the repeater 102 with 168 bit elements, and expands to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i==0 i=others

[0072] the coder 104 carries out LDPC coding on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335];

[0073] the master code generator 105 combines the signalling sequence a and the 336-bit check data packet b into a 416-bit master code data packet s=[a, b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0074] the rate matcher 106 constructs a 672-bit coded data packet e by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

[0075] In the second mode, when there is a first-class filler 101,

[0076] the first-class filler 101 fills the signalling sequence a with 4 bit elements into a first 84-bit data packet;

[0077] the repeater 102 splits the first data packet into two 42-bit sub-data packets, and then repeats each sub-data packet for one time respectively;

[0078] the second-class filler 103 fills the data packet repeated by the repeater 102 with 168 bit elements, and expands to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0079] the coder 104 carries out LDPC coding on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335];

[0080] the master code generator 105 combines the signalling sequence a and the 336-bit check data packet b into a 416-bit master code data packet s=[a, b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0081] the rate matcher 106 constructs a 672-bit coded data packet e by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Second Example

[0082] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00007 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 39 −1 13 −1 22 −1 9 20 −1 −1 −1 −1 −1 −1 −1 1 17 −1 −1 26 −1 2 −1 18 40 4 −1 −1 −1 −1 −1 −1 2 34 −1 24 −1 28 −1 19 −1 −1 8 29 −1 −1 −1 −1 −1 3 −1 36 6 −1 14 −1 38 −1 −1 −1 16 30 −1 −1 −1 −1 4 −1 33 −1 39 −1 24 −1 27 18 −1 −1 18 33 −1 −1 −1 5 9 −1 30 −1 −1 4 −1 36 −1 12 −1 −1 24 0 −1 −1 6 26 −1 12 −1 0 −1 15 −1 −1 −1 32 −1 −1 −1 0 −1 7 −1 30 −1 10 28 −1 34 −1 −1 −1 −1 11 −1 −1 −1 0

[0083] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. The coder 104 is a (16×42, 8×42) LDPC coder, the basic parity check matrix is an 8×16 matrix, the expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39] (k=40 bits), and when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), there are two processing modes.

[0084] In the first mode, when there is not a first-class filler 101,

[0085] the repeater 102 repeats the signalling sequence f for one time, and then expands to obtain an 84-bit data packet;

[0086] the second-class filler 103 fills the data packet expanded by the repeater 102 with 252 bit elements, and expands to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i==0 i=others

[0087] the coder 104 carries out LDPC coding on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335];

[0088] the master code generator 105 combines the signalling sequence a and the 336-bit check data packet b into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and

[0089] the rate matcher 106 constructs a 672-bit coded data packet h by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

[0090] In the second mode, when there is a first-class filler 101,

[0091] the first-class filler 101 fills the signalling sequence f with 2 bit elements into a first 42-bit data packet;

[0092] the repeater 102 repeats the first data packet for one time;

[0093] the second-class filler 103 fills the data packet repeated by the repeater 102 with 252 bit elements, and expands to obtain a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335], d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i=0 i=others

[0094] the coder 104 carries out LDPC coding on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335];

[0095] the master code generator 105 combines the signalling sequence a and the 336-bit check data packet b into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and

[0096] the rate matcher 106 constructs a 672-bit coded data packet h by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

Third Embodiment

[0097] Based on the apparatus, the embodiment of the disclosure also implements a method for supporting low bit rate coding. As shown in FIG. 3, the method mainly includes the steps as follows.

[0098] Step 301: A source data packet to be coded is repeated for i times, i being a positive integer.

[0099] Repeating the source data packet to be coded for i times can be implemented in two modes, and in the first mode, the source data packet to be coded is directly repeated for i times; and

[0100] in the second mode, the source data packet includes j sub-data packets, the j sub-data packets are repeated for i times respectively, j is a positive integer, and i may be 1, 2, 3, 4, 5 or 6 generally.

[0101] Step 302: The data packet repeated for i times is coded, coding being LDPC coding, Turbo coding or convolutional coding.

[0102] Here, coding may adopt (nb×z, kb×z) LDPC coding, and a master code data packet is obtained by coding, where nb is a column number of a basic parity check matrix, (nb−kb) is a row number of the basic parity check matrix, z is an expansion factor, and z, nb and kb are positive integers greater than 0. Before LDPC codes are coded, the basic parity check matrix is read, and then values of r non −1 element in the basic parity check matrix are set as −1, where r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

[0103] The check data packet will be obtained after Step 202, the method further includes that: rate matching is carried out on the master code data packet so as to obtain an N-bit coded data packet, N being a positive integer representative of a code length.

[0104] The steps of the method for supporting low bit rate LDPC code coding according to the present embodiment are illustrated below by means of four specific examples.

First Example

[0105] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00008 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0106] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.71] (k=72 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=1024 bits), the signalling sequence a is repeated for one time, and a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=a.sub.i-180 i=180,181, . . . ,209

d.sub.i=a.sub.i-222 i=222,223, . . . ,293

d.sub.i=a.sub.i-264 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0107] then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 408-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.407]; and

[0108] finally, a 1024-bit coded data packet e is constructed by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,407

e.sub.j=s.sub.j-408 j=408,409, . . . ,815

e.sub.j=s.sub.j-816 j=816,817, . . . ,1023.

Second Example

[0109] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00009 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0110] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), the signalling sequence a is repeated for one time, and a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0111] then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a, b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0112] finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Third Example

[0113] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00010 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 23 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 36 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 18 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0114] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, the basic parity check matrix is an 8×16 matrix, the expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39] (k=40 bits), and when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), the signalling sequence f is repeated for one time, and a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i=0 i=others

[0115] then, LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

Fourth Example

[0116] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0117] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), the signalling sequence a is repeated for one time, and a 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0118] then, an element ‘0’ in the second row and the sixth column in the basic parity check matrix is modified into ‘−1’ first, and the modified basic parity check matrix is as follows:

TABLE-US-00012 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 −1 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0119] LDPC coding is carried out on the data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0120] finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Fourth Embodiment

[0121] The embodiment of the disclosure implements a method for supporting low bit rate coding. The basic steps are the same as those of the third embodiment. In the present embodiment, before Step 301, a first data packet can be obtained by filling a source data packet to be coded with q1 elements and then expanding, q1 being a positive integer.

[0122] Here, repeating the source data packet to be coded for i times can be implemented in two modes, and in the first mode, the first data packet is directly repeated for i times; and

[0123] in the second mode, the first data packet is split into j sub-data packets, each sub-data packet is repeated for i times respectively, j is a positive integer, and i may be 1, 2, 3, 4, 5 or 6 generally.

[0124] The method according to the present embodiment further includes that: the data packet repeated for i times is filled with q2 elements so as to obtain a second data packet by expansion.

[0125] According to the present embodiment, in Step 302, (nb×z, kb×z) LDPC coding is adopted, and a check data packet is obtained by coding, where nb is a column number of a basic parity check matrix, (nb−kb) is a row number of the basic parity check matrix, z is an expansion factor, and z, nb and kb are positive integers greater than 0. Before LDPC codes are coded, the basic parity check matrix is read, and then values of r non −1 element in the basic parity check matrix are set as −1, where r is an integer which is greater than or equal to 0 and is smaller than r0, and r0 is the number of non −1 elements in an original basic parity check matrix.

[0126] The method according to the present embodiment further includes that: the check data packet and the source data packet are combined into a master code data packet, and after the master code data packet is obtained, an N-bit coded data packet can be obtained by carrying out rate matching on the master code data packet.

[0127] The steps of the method for supporting low bit rate LDPC code coding according to the present embodiment are illustrated below by means of two specific examples.

First Example

[0128] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00013 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 0 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 13 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 37 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0129] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, a source data packet to be coded is a signalling sequence a=[a.sub.0, a.sub.1, a.sub.2, . . . , a.sub.79] (k=80 bits), and when LDPC coding is carried out on the signalling sequence a using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet e (n=672 bits), there are two processing modes.

[0130] In the first mode,

[0131] firstly, the signalling sequence a is repeated for one time, and a 168-bit data packet is obtained by expansion;

[0132] then, the data packet is filled with 168 bit elements, and a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0133] then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0134] finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

[0135] In the second mode,

[0136] firstly, the signalling sequence a is filled with 4 bit elements to expand into a first 84-bit data packet, the first data packet is split into two 42-bit sub-data packets, and then each sub-data packet is repeated for one time respectively;

[0137] then, the repeated data packet is filled with 168 bit elements, and a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=a.sub.i-172 i=172,173, . . . ,209

d.sub.i=a.sub.i-214 i=214,215, . . . ,293

d.sub.i=a.sub.i-256 i=294,295, . . . ,335;

d.sub.i=0 i=others

[0138] then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 416-bit master code data packet s=[a,b]=[s.sub.0, s.sub.1, . . . , s.sub.415]; and

[0139] finally, a 672-bit coded data packet e is constructed by the master code data packet s, e being:

e.sub.j=s.sub.j j=0,1, . . . ,415

e.sub.j=s.sub.j-416 j=416,417, . . . ,671.

Second Example

[0140] Given that a basic parity check matrix Hb.sub.8×16 is as follows:

TABLE-US-00014 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B 0 −1 0 −1 0 −1 0 −1 0 0 −1 −1 −1 −1 −1 −1 −1 1 0 −1 −1 34 −1 12 −1 36 18 23 −1 −1 −1 −1 −1 −1 2 8 −1 0 −1 0 −1 0 −1 −1 36 0 −1 −1 −1 −1 −1 3 −1 16 40 −1 32 −1 22 −1 −1 −1 19 0 −1 −1 −1 −1 4 −1 20 −1 22 −1 2 −1 28 32 −1 −1 21 0 −1 −1 −1 5 30 −1 18 −1 −1 14 −1 30 −1 18 −1 −1 31 0 −1 −1 6 40 −1 12 −1 38 −1 6 −1 −1 −1 26 −1 −1 13 0 −1 7 −1 24 −1 20 10 −1 2 −1 −1 −1 −1 18 −1 −1 5 0

[0141] A bit rate corresponding to the shown basic parity check matrix Hb.sub.8×16 is 1/2, an expansion factor z=42, a matrix row number is 8, a matrix column number is 16, numbers shown in left is row indexes, uppermost numbers are column indexes, a letter ‘A’ represents a system bit part matrix, and a letter ‘B’ represents a check bit part matrix. (16×42, 8×42) LDPC coding is adopted, the basic parity check matrix is an 8×16 matrix, the expansion factor z=42, a source data packet to be coded is a signalling sequence f=[f.sub.0, f.sub.1, . . . , f.sub.39] (k=40 bits), and when LDPC coding is carried out on the signalling sequence f using a 1/2 bit rate LDPC code basic parity check matrix to obtain a coded data packet h (n=672 bits), there are two processing modes.

[0142] In the first mode,

[0143] firstly, the signalling sequence f is repeated for one time, and an 84-bit data packet is obtained by expansion; the data packet is filled with 252 bit elements, and a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained, d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i=0 i=others

[0144] then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and

[0145] finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

[0146] In the second mode,

[0147] firstly, the signalling sequence f is filled with 2 bit elements to expand into a first 42-bit data packet, and the first data packet is repeated for one time;

[0148] then, the repeated data packet is filled with 252 bit elements, and a second 336-bit data packet d=[d.sub.0, d.sub.1, . . . , d.sub.335] is obtained by expansion, d being as follows:

d.sub.i=f.sub.i-254 i=254,255, . . . ,293

d.sub.i=f.sub.i-296 i=296,297, . . . ,335;

d.sub.i=0 i=others

[0149] then, LDPC coding is carried out on the second data packet d to obtain a check data packet b=[b.sub.0, b.sub.1, . . . , b.sub.335], and the signalling sequence a and the 336-bit check data packet b are combined into a 376-bit master code data packet g=[f,b]=[g.sub.0, g.sub.1, . . . , g.sub.375]; and

[0150] finally, a 672-bit coded data packet h is constructed by the master code data packet g, h being:

h.sub.j=g.sub.j i=0,1, . . . ,375

h.sub.j=g.sub.j-376 i=376,417, . . . ,671.

[0151] If the method for supporting low bit rate coding in the embodiment of the disclosure is implemented in a form of a software function module and when being sold or used as an independent product, the product may also be stored in a computer readable storage medium. Based on this understanding, those skilled in the art shall understand that the embodiments of the disclosure may be provided as a method, a system or a computer program product. Thus, forms of complete hardware embodiments, complete software embodiments or embodiments integrating software and hardware may be adopted in the disclosure. Moreover, a form of the computer program product implemented on one or more computer available storage media containing computer available program codes may be adopted in the disclosure. The storage media include, but are not limited to, a U disk, a mobile hard disk, a Read-Only Memory (ROM), a magnetic disk memory, a CD-ROM, an optical memory and the like.

[0152] The disclosure is described with reference to flowcharts and/or block diagrams of the method, the device (system) and the computer program product according to the embodiments of the disclosure. It will be appreciated that each flow and/or block in the flowcharts and/or the block diagrams and combination of the flows and/or the blocks in the flowcharts and/or the block diagrams may be implemented by computer program instructions. These computer program instructions may be provided to a general computer, a dedicated computer, an embedded processor or processors of other programmable data processing devices to generate a machine, such that an apparatus for implementing functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams is generated via instructions executed by the computers or the processors of the other programmable data processing devices.

[0153] These computer program instructions may also be stored in a computer readable memory capable of guiding the computers or the other programmable data processing devices to work in a specific mode, such that a manufactured product including an instruction apparatus is generated via the instructions stored in the computer readable memory, and the instruction apparatus implements the functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.

[0154] These computer program instructions may also be loaded to the computers or the other programmable data processing devices, such that processing implemented by the computers is generated by executing a series of operation steps on the computers or the other programmable devices, and therefore the instructions executed on the computers or the other programmable devices provide a step of implementing the functions designated in one or more flows of the flowcharts and/or one or more blocks of the block diagrams.

[0155] Accordingly, an embodiment of the disclosure also provides a computer storage medium. A computer program is stored therein and is configured to execute the method for supporting low bit rate coding according to the embodiment of the disclosure.

[0156] The above is only the preferred embodiments of the disclosure and is not used to limit the protective scope of the disclosure.

INDUSTRIAL APPLICABILITY

[0157] All the embodiments of the disclosure are integrated. By repeating a source data packet to be coded for several times and then coding the data packet, coding gains can be fully utilized, and the coding and decoding performances of a coding and decoding system under a lower bit rate are improved.