H03M13/616

Method and apparatus for wirelessly communicating over a noisy channel with a variable codeword length polar code to improve transmission capacity

Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs). For the most part, the provided embodiments can be implemented with nearly all available current encoding/decoding polar code techniques.

LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME
20180006663 · 2018-01-04 ·

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 3/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

METHOD AND SYSTEM FOR POLAR CODE CODING
20230231577 · 2023-07-20 ·

A system and method for polar code coding with information bits placed in particular bit indexes are disclosed herein. In one embodiment, a method for channel coding includes: associating, by a polar code encoder, a first bit sequence with first bit indexes of a polar code input; associating, by the polar code encoder, a second bit sequence with second bit indexes, wherein the first bit indexes have a higher reliability than the second bit indexes; and encoding, by the polar code encoder, both the first bit sequence and the second bit sequence using a generator matrix to generate encoded bits.

Storage network with enhanced data access performance
11704184 · 2023-07-18 · ·

A method for execution by a storage network begins by issuing a decode threshold number of read requests for a set of encoded data slices to a plurality of storage units of a set of storage units and continues by determining whether less than a decode threshold number of read requests has been received in a time window. The method continues by identifying one or more encoded data slices encoded data slices associated with read requests of the decode threshold number of read requests that have not been received and for an encoded data slice of the one or more encoded data slices, issuing a priority read request to a storage unit storing a copy of the encoded data slice. The method then continues by receiving a response from the storage unit storing the copy of the encoded data, where the storage unit storing the copy of the encoded data slice is adapted to delay one or more maintenance tasks in response to the priority read request.

Processing of data

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

BCH FAST SOFT DECODING BEYOND THE (D-1)/2 BOUND
20230223958 · 2023-07-13 ·

A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has τ=t+r errors for some r≥1; computing a minimal monotone basis {λ.sub.i(x)}.sub.1≤i≤r+1.Math.F[x] of an affine space V={λ(x)∈F[x]:λ(x).Math.S(x)=λ′(x) (mod x.sup.2t), λ(0)=1, deg(λ(x)≤t+r}, wherein λ(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A≡(λ.sub.j(β.sub.i)).sub.i∈[w],j∈[r+1], wherein W={β.sub.1, . . . , β.sub.w} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

Method and apparatus for signal receiving and deinterleaving

A signal receiving method include: demodulating a signal received from a transmitting apparatus to generate values based on 1024-quadrature amplitude modulation (QAM); splitting the values into a plurality of groups; deinterleaving the plurality of groups based on a preset interleaving order; and decoding values of the deinterleaved plurality of groups based on a low density parity check (LDPC) code, a code rate of the LDPC code being 6/15 and a code length of the LDPC code being 64800, wherein the plurality of groups are deinterleaved based on a predetermined equation.

Method and system for providing minimal aliasing error correction code

Disclosed is a method and system for providing a minimal aliasing error correction code. In constructing a single error correction (SEC) code by constructing a parity check matrix H for a data length k applied to a device, as the SEC code is designed to be valid and minimize generation of aliasing by checking some bits rather than all bits when nonzero binary column matrices different from each other are arranged in the parity check matrix, destruction of information can be prevented, and reliability of a device applying the SEC, such as DRAM or the like, can be improved.

Integrated circuit for reception apparatus

Disclosed are an encoder, a transmission device, and an encoding method with which the transmission amount is reduced and a deterioration in transmission efficiency is suppressed while improving reception quality when QC-LDPC or a like block encoding is used. A puncture pattern setting unit (620) searches for a puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of a sub block matrix that forms a check matrix (H) of a QC-LDPC code, and a puncture unit (data reduction unit) (630) switches the puncture pattern for each integral multiple of the number of columns or for each divisor of the number of columns of the sub block matrix that forms the check matrix of the QC-LDPC code.