METHOD FOR THERMO-MECHANICAL STRESS REDUCTION IN SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE

Abstract

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10.sup.−6 m.) and approximately 10 micron (10.sup.−5 m.) from each one of said converging sides landing on an underlying metal layer.

Claims

1. A method, comprising: manufacturing a semiconductor device, the manufacturing including: providing a passivation layer over a dielectric layer; providing a metallization on the passivation layer, the metallization having a corner; and providing a via through said passivation layer and said dielectric layer near said corner.

2. The method of claim 1, wherein providing said via includes providing the via without electrical connections to an active device.

3. The method of claim 1, wherein: said corner includes converging sides; and providing said via includes providing said via at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.

4. The method of claim 1, wherein providing said metallization as a Cu metallization.

5. The method of claim 1, wherein providing said via includes providing the via as a via landing on an underlying metal layer.

6. The method of claim 1, further comprising forming a barrier layer lining the via and underlying the metallization.

7. A semiconductor device, comprising: a dielectric layer; a passivation layer over the dielectric layer; a metallization having a corner; and a via through said passivation layer and said dielectric layer near said corner.

8. The semiconductor device of claim 7, wherein said via is without electrical connections to an active device.

9. The semiconductor device of claim 7, wherein said corner includes converging sides, wherein said via is at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.

10. The semiconductor device of claim 7, wherein said metallization includes a Cu metallization.

11. The semiconductor device of claim 7, further comprising an underlying metal layer underlying the dielectric layer, wherein said via includes a via landing on the underlying metal layer.

12. The semiconductor device of claim 7, further comprising a barrier layer lining the via and underlying the metallization.

13. A semiconductor device, comprising: a dielectric layer; a passivation layer over the dielectric layer; a metallization having a corner; a via through said passivation layer and said dielectric layer near said corner, wherein the metallization extends in the via; and a barrier layer lining the via and extending between the metallization and the passivation layer.

14. The semiconductor device of claim 13, wherein said via is without electrical connections to an active device.

15. The semiconductor device of claim 13, wherein said corner includes converging sides, wherein said via is at a distance between approximately 1 micron and approximately 10 micron from each one of said converging sides.

16. The semiconductor device of claim 13, wherein said metallization includes a Cu metallization.

17. The semiconductor device of claim 13, further comprising an underlying metal layer underlying the dielectric layer, wherein said via includes a via landing on the underlying metal layer.

Description

DETAILED DESCRIPTION

[0026] In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured.

[0027] Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

[0028] The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

[0029] Semiconductor device metallizations such as, e.g., Cu structures with a Ni—Pd, Ni—Pd—Au, Ni—Au and/or capping layer Ni-based, possibly involving a Cu activation process prior to electroless deposition represent an extensive area of technical investigation.

[0030] Exemplary of related activity are, e.g.: [0031] P. K. Yee, et al.: “Palladium-Copper Inter-diffusion during Copper Activation for Electroless Nickel Plating Process on Copper Power Metal”, 2014 IEEE 21st International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), [0032] U.S. Pat. No. 6,093,631 B1, or [0033] U.S. Pat. No. 6,413,863 B1.

[0034] FIG. 1 is exemplary of a possible arrangement of a metallization 10 in a semiconductor device such as, e.g., a Cu wire bonding pad provided on a substrate such as a substrate with a passivation layer (e.g., SiN, SiC) 12 over a dielectric layer 22, with a layer 14 (e.g., TiW, Ta, TaN) acting as a barrier under the metallization 10, e.g., a Cu-RDL (re-distribution layer) structure.

[0035] In one or more embodiments, a metallization (Cu-RDL structure) 10 as exemplified in FIG. 2 may exhibit two sides 10a converging towards a corner 10b. In one or more embodiments, the corner 10b may include an, e.g., at least slightly beveled vertex (or corner proper).

[0036] It was observed that stresses such as passivation stress may arise in the SiN or SiC upper surface at the edge (foot) of, e.g., Cu-RDL structure with a higher value at the Cu_RDL corner 10b, e.g., at a triple point TP (see FIG. 1) where the barrier layer 14 underlying the Cu-RDL structure 10 is in contact with a (e.g., Ni-based) capping layer 20 provided on the metallization 10.

[0037] In one or more embodiments at least one via 16 (that is a through hole in the passivation layer 12 and the dielectric layer 22) may be provided under the metallization 10 landing on an underlying metal layer 24.

[0038] In one or more embodiments, the via 16 may include a “dummy” via, namely a via without electrical connection to any active device.

[0039] In one or more embodiments as exemplified in FIG. 1, the metallization 10 may extend into the via 16.

[0040] In one or more embodiments as exemplified in FIG. 1, the barrier layer 14 (e.g., TiW, Ta, TaN) acting as a barrier under the metallization 10 may form a lining layer that lines the via 16.

[0041] In one or more embodiments, the via 16 may be a, e.g., re-distribution layer (RDL) via landing on what is currently referred to as Metal n−1 (underlying metal layer 24).

[0042] In one or more embodiments, the via 16 may be arranged as close as possible to the corner 10b.

[0043] In one or more embodiments this may involve providing the via 16, which may be provided by any known means for that purpose, at a distance d′, d″ between approximately 1 micron (10.sup.−6 m) and approximately 10 micron (10.sup.−5 m) from each of the converging sides 10a which jointly define the corner portion 10b of the metallization 10.

[0044] In one or more embodiments such a measure was found to improve passivation robustness by operating only on the layout rules of the metallization without any process modification, that is without appreciable impact on final product performance.

[0045] Experiments performed with the applicant company have demonstrated that such a placement of vias 16 exhibit correlation with passivation fails occurrence, with the number of the fails reduced (and notionally made nil) at those locations where vias 16 are provided.

[0046] Consequently, it may be concluded the presence of vias may effectively decrease passivation layer stress.

[0047] Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been disclosed merely by way of example, without departing from the extent of protection.

[0048] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.