An extreme ultraviolet light generator includes a collector including a first focus and a second focus, a droplet feeder configured to provide a source droplet toward the first focus of the collector, a laser generator configured to irradiate a laser toward the first focus of the collector, an airflow controller between the first focus and the second focus of the collector, the airflow controller having a ring shape, and the airflow controller including at least one slit, and a first part and a second part hinged to each other, and a control gas feeder configured to provide a control gas towards the at least one slit of the airflow controller.

An extreme ultraviolet light generator includes a collector including a first focus and a second focus, a droplet feeder configured to provide a source droplet toward the first focus of the collector, a laser generator configured to irradiate a laser toward the first focus of the collector, an airflow controller between the first focus and the second focus of the collector, the airflow controller having a ring shape, and the airflow controller including at least one slit, and a first part and a second part hinged to each other, and a control gas feeder configured to provide a control gas towards the at least one slit of the airflow controller.

Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

A method for forming etched features in a layer of a first material is provided. A layer of a second material is deposited over the layer of the first material. An alloy layer of the first material and the second material is formed between the layer of the first material and the layer of the second material. The layer of the first material is selectively etched with respect to the alloy layer, using the alloy layer as a hardmask.

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

There is provided a shower head disposed in a processing container where a substrate is accommodated and configured to discharge a gas to the substrate in a shower pattern, comprising: a main body portion having a facing surface facing a stage disposed in the processing container to place the substrate thereon; a covering section that covers a surface formed on an opposite side of the facing surface of the main body portion, and forms, between the surface and the covering section, an exhaust space that is exhausted by an exhaust mechanism; a plurality of exhaust hole forming regions disposed on the facing surface apart from each other and each having a plurality of exhaust holes; a plurality of discharge holes disposed for each of the exhaust hole forming regions on the facing surface to surround each of the plurality of exhaust hole forming regions and configured to discharge the gas; a diffusion space disposed to be shared by the plurality of discharge holes, where the gas supplied to the main body portion is diffused to be supplied to each of the plurality of discharge holes; and an exhaust path disposed in the main body portion to be connected to the exhaust holes and opened to the exhaust space in order to exhaust the gas discharged from the discharge holes into the exhaust space.

Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.

Provided is a method of SiC wafer processing, and the method includes the following steps. A SiC wafer is provided, and the SiC wafer has a first surface and an opposing second surface. A fine grinding process is performed on the first surface and the second surface of the SiC wafer. A dry etching process is performed on the first surface and the second surface of the SiC wafer to make the roughness of the first surface and the second surface 2.5 nm or less. After the dry etching process, a polishing process is performed on the first surface and the second surface of the SiC wafer.

A method for manufacturing a shallow trench isolation structure includes: providing a substrate and forming multiple first trenches in the substrate, in which a cross-sectional width of each first trench increases downward along a vertical direction; forming a continuous first isolation layer on a top of the substrate and inner sides of the multiple first trenches by a deposition process, in which parts of the first isolation layer located in the first trenches form second trenches, and in which a cross-sectional width of each second trench remains constant downward along the vertical direction; and forming a continuous second isolation layer on a surface of the first isolation layer by an ISSG process, in which parts of the second isolation layer located in the second trenches completely fill up the second trenches.