Semiconductor device

Abstract

Aspects of the invention provide a compact semiconductor device having a surge protection element, which can reliably protect against surge and is unlikely to be affected by manufacturing variation. By forming a parasitic n-p-n transistor on a guard ring, and adopting the parasitic n-p-n transistor as a surge protection element, it is possible to provide a compact semiconductor device having a surge protection element. Also, by adopting the parasitic n-p-n transistor as a surge protection element, it is possible to reduce the operating resistance in comparison with when using a parasitic n-p-n transistor as a surge protection element, and thus possible to improve the surge protection function. Further, by providing one surge protection element on the guard ring, rather than providing a surge protection element in each cell, it is possible minimize the effect of manufacturing variation (i.e., in-plane variation) on the surge protection function.

Claims

1. A semiconductor device, comprising: a second conductivity type first semiconductor region disposed in a surface layer of a first conductivity type semiconductor substrate; an active region disposed in a surface layer of the first semiconductor region, the active region being part of a protected device; a first conductivity type second semiconductor region, of a higher concentration than the semiconductor substrate, disposed enclosing the active region, straddling, and in contact with, the first semiconductor region and semiconductor substrate; a first conductivity type third semiconductor region, of a higher concentration than the second semiconductor region, disposed in a surface layer of the second semiconductor region; and a second conductivity type fourth semiconductor region disposed in a surface layer of the second semiconductor region between the third semiconductor region and active region, wherein a guard ring is configured of the second semiconductor region and third semiconductor region, a parasitic bipolar transistor is configured of the fourth semiconductor region, second semiconductor region, and first semiconductor region, and the parasitic bipolar transistor forms an electrostatic discharge (ESD) surge protection element.

2. A semiconductor device, comprising: a second conductivity type first semiconductor region selectively disposed in a surface layer of a first conductivity type semiconductor substrate; a first conductivity type plurality of second semiconductor regions disposed in a surface layer of the first semiconductor region, the plurality of second semiconductor regions being part of a protected device; a plurality of second conductivity type drain regions, disposed distanced from the second semiconductor region in a surface layer of the first semiconductor region, disposed alternately with the second semiconductor region; a second conductivity type source region disposed in a surface layer of the second semiconductor region; a first conductivity type contact region disposed in contact with the source region in a surface layer of the second semiconductor region; an oxide film selectively disposed on the first semiconductor region; a gate electrode disposed across a gate insulating film on the second semiconductor region sandwiched by the first semiconductor region and source region; a drain electrode connected to the drain region; a source electrode connected to the source region and contact region; a first conductivity type third semiconductor region, disposed straddling, and in contact with, the first semiconductor region and semiconductor substrate, and disposed so as to enclose the second semiconductor region group; a first conductivity type fourth semiconductor region, of a higher concentration than the third semiconductor region, disposed in a surface layer of the third semiconductor region; a second conductivity type fifth semiconductor region disposed in a surface layer of the third semiconductor region between the fourth semiconductor region and second semiconductor region; and a ground electrode connected to the fourth semiconductor region and fifth semiconductor region, wherein the fifth semiconductor region is disposed opposing the drain region disposed between the second semiconductor region and third semiconductor region, a guard ring is configured of the first semiconductor region and third semiconductor region, and an electrostatic discharge (ESD) surge protection element is configured of a parasitic bipolar transistor formed of the first semiconductor region, third semiconductor region, and fifth semiconductor region.

3. The semiconductor device according to claim 2, wherein the distance between the third semiconductor region and drain region is shorter than the distance between the second semiconductor region and drain region.

4. The semiconductor device according to claim 2, wherein the second semiconductor region, drain region, and fifth semiconductor region are alternately disposed in parallel in an elongated planar form, and the width in a direction perpendicular to the longitudinal direction of the fifth semiconductor region is greater than the width in a direction perpendicular to the longitudinal direction of the source region.

5. The semiconductor device according to claim 3, wherein the second semiconductor region, drain region, and fifth semiconductor region are alternately disposed in parallel in an elongated planar form, and the width in a direction perpendicular to the longitudinal direction of the fifth semiconductor region is greater than the width in a direction perpendicular to the longitudinal direction of the source region.

6. The semiconductor device according to claim 4, wherein the planar form of the fourth semiconductor region is insular, and the fifth semiconductor region extends into gaps in the insular fourth semiconductor region.

7. The semiconductor device according to claim 2, wherein the diffusion depth of the third semiconductor region is selectively shallow.

8. The semiconductor device according to claim 2, wherein the drain region is replaced with a first conductivity type collector region and a lateral MOS field effect transistor is changed to a lateral insulated gate bipolar transistor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a main portion plan view of a semiconductor device 100 according to a first working example (or embodiment) of the invention;

(2) FIGS. 2A and 2B are enlarged views of an A portion of FIG. 1, wherein FIG. 2A is a main portion plan view of an output stage MOSFET, and FIG. 2B is a main portion sectional view taken along an X-X line of FIG. 2A;

(3) FIG. 3 is a main portion plan view of electrode wiring of the semiconductor device 100 of FIG. 1;

(4) FIG. 4 is a current (Id)-voltage (Vd) characteristic diagram for an output stage MOSFET 101;

(5) FIG. 5 is a main portion plan view of a semiconductor device 200 according to a second working example (or embodiment) of the invention;

(6) FIG. 6 is a main portion sectional view of a semiconductor device 300 according to a third working example (or embodiment) of the invention;

(7) FIG. 7 is a main portion plan view of a conventional semiconductor device 500;

(8) FIGS. 8A and 8B are enlarged views of a B portion of FIG. 7, wherein FIG. 8A is a main portion plan view of an output stage MOSFET 501, and FIG. 8B is a main portion sectional view taken along an X-X line of FIG. 8A;

(9) FIG. 9 is a main portion plan view of electrode wiring of the semiconductor device 500 of FIG. 9; and

(10) FIG. 10 is a current (Id)-voltage (Vd) characteristic diagram for the output stage MOSFET 501.

DETAILED DESCRIPTION

(11) Embodiments of the invention are described below using the following working examples.

WORKING EXAMPLE 1

(12) FIG. 1 is a main portion plan view of a semiconductor device 100 according to a first working example of the invention. FIGS. 2A and 2B are enlarged views of an A portion of FIG. 1, wherein FIG. 2A is a main portion plan view of an output stage MOSFET, and FIG. 2B is a main portion sectional view taken along an X-X line of FIG. 2A. FIG. 3 is a main portion plan view of electrode wiring of the semiconductor device 100 of FIG. 1.

(13) In FIGS. 1 to 3, the semiconductor device 100 has a surge protection element 16, and the surge protection element 16 is configured of a parasitic transistor 15 formed on a guard ring 17. The surge protection element 16 is an ESD protection element, or the like.

(14) The semiconductor device 100 includes an n-type well region 2 of, for example, a dose of in the region of 3×10.sup.12 cm.sup.−2 and a diffusion depth of in the region of 8 μm disposed in a surface layer of a p-type semiconductor substrate 1 of a resistivity of, for example, in the region of 100 Ω.Math.cm to 150 Ω.Math.cm. Also, the semiconductor device 100 includes a plurality of (lateral n-type MOSFET) stripe-form p-type well regions 4 of, for example, a dose of in the region of 1.6×10.sup.13 cm.sup.−2 and a diffusion depth of in the region of 3 disposed in the n-type well region 2 and configuring a cell 4a of an output stage MOSFET 101. Also, the semiconductor device 100 includes stripe-form n-type source regions 6 of, for example, a dose of in the region of 2×10.sup.15 cm.sup.−2 and a diffusion depth of in the region of 0.5 μm, disposed in a surface layer of the p-type well region 4. Also, the semiconductor device 100 includes a stripe-form p-type contact region 7 disposed sandwiched by the n-type source regions 6. The semiconductor device 100 includes a gate electrode 11, formed of polysilicon, disposed across a gate oxide film 25 on the p-type well region 4 sandwiched by the n-type source region 6 and n-type well region 2, and a stripe-form n-type drain region 5 disposed distanced from the p-type well region 4. A LOCOS 10 (selective oxide film) is disposed between the p-type well region 4 and n-type drain region 5. The semiconductor device 100 includes a p-type well region 3 of, for example, a dose of in the region of 1.6×10.sup.13 cm.sup.−2 and a diffusion depth of in the region of 3 μm, disposed so as to enclose the p-type well region 4 group, a ring-form p.sup.+ region 9 disposed in a surface layer of the p-type well region 3, and a stripe-form n.sup.+ region 8 of, for example, a dose of in the region of 2×10.sup.15 cm.sup.−2 and a diffusion depth of in the region of 0.5 μm, disposed so as to be in contact with the p.sup.+ region 9 and to oppose the p-type well region 4 on the inner side of the p.sup.+ region 9. The guard ring 17 is configured of the p-type well region 3 and p.sup.+ region 9. The p.sup.+ region 9 has a function of stabilizing the potential of the guard ring 17 at the ground potential. Also, in FIG. 1, the n.sup.+ region 8 is disposed so as to oppose the stripe-form n-type drain region 5, and so as to be the same length as a length V of the n-type drain region 5. However, the n.sup.+ region 8 may also be disposed in a ring-form, or disposed divided into a plurality. When the n.sup.+ region 8 is disposed in a ring-form, AI wiring (drain electrode wiring 12, or the like) passes over the n.sup.+ region 8, as shown in FIG. 3, and the potential of the n.sup.+ region 8 is liable to become unstable, which is not desirable.

(15) The parasitic transistor 15 is configured of the n.sup.+ region 8, p-type well region 3, and n-type well region 2, and the parasitic transistor 15 forms the surge protection element 16.

(16) An n-type well region 21 forming an integrated circuit 102 (an internal circuit) is formed distanced from the n-type well region 2 in a surface layer of the p-type semiconductor substrate 1. The n-type well region 21 is in contact with the p-type well region 3, and a p.sup.+ region 20 is disposed in the p-type well region 3 between the n-type well region 2 and n-type well region 21. The p.sup.+ region 20 is an isolation region that electrically isolates the output stage MOSFET 101 and integrated circuit 102.

(17) A distance L2 of the n-type well region 2 (drift region) between the p-type well region 3 of the guard ring and the n-type drain region 5 of the output stage MOSFET 101 is shorter than a distance L1 of the n-type well region 2 between the p-type well region 4 and n-type drain region 5 of the output stage MOSFET 101. This is in order that avalanche will occur in a p-n junction A between the p-type well region 3 and n-type well region 2 on the guard ring 17 side before occurring in a p-n junction B between the p-type well region 4 and n-type well region 2 when a surge such as an ESD is applied to the n-type drain region 5. By avalanche occurring first in the p-n junction A between the p-type well region 3 and n-type well region 2 of the guard ring 17, the parasitic transistor 15 formed on the guard ring 17 starts operating, and can reliably protect the semiconductor device 100 from the surge.

(18) Also, as described above, the p.sup.+ region 9 spreads beyond the p-type well region 3, and encloses an active region 18 of the output stage MOSFET 101. The cell 4a configuring the active region 18 of the output stage MOSFET 101 ranges from the center of the p-type contact region 7 to the n-type drain region 5, is configured of the n-type source region 6, p-type well region 4, n-type drift region (n-type well region 2), and n-type drain region 5, and a plurality thereof are disposed.

(19) The output stage MOSFET 101 is a lateral n-type channel MOSFET, each cell 4a is of a stripe-form, and the gate structure is a planar structure.

(20) As described above, the parasitic transistor 15 is disposed on the guard ring 17, and the parasitic transistor 15 is used as the surge protection element 16, which is an ESD protection element or the like. By the parasitic transistor 15 being turned on when a surge such as an ESD is applied, it is possible to protect the integrated circuit 102, which is the internal circuit, from the surge.

(21) As the surge protection element 16 is formed on the guard ring 17 of the output stage MOSFET 101, it is possible to reduce the chip area in comparison with when forming a surge protection element in a place other than the output stage MOSFET 101.

(22) Also, as one surge protection element 16 is provided on the guard ring 17, rather than a surge protection element 16 being provided in each of the plurality of cells 4a configuring the output stage MOSFET 101, the surge protection function is unlikely to be affected by structural variation.

(23) Also, as the surge protection element 16 is formed on the guard ring 17, the formation of the surge protection element 16 does not affect the characteristics of the output stage MOSFET 101.

(24) Also, as the dynamic resistance of the surge protection element 16 of the parasitic transistor 15 is low in comparison with a conventional parasitic diode 65, it is possible to reliably protect the output stage MOSFET 101 and the integrated circuit 102, which forms the internal circuit, from surge.

(25) In FIG. 3, ground electrode wiring 14, gate wiring 11a, source electrode wiring 13, and the drain electrode wiring 12 are formed of aluminum or aluminum alloy wiring, and the wirings are disposed on an unshown interlayer insulating film on the n-type well region 2 or LOCOS 10. Each electrode wiring (12, 13, and 14) and semiconductor region (5, 6, 7, 8, and 9), and the gate electrode 11 and gate wiring 11a, are connected via a contact hole formed in the interlayer insulating film (not shown). Although not shown, the drain electrode 12 connected to the n-type drain region 5 and the source electrode 13 connected to the n-type source region 6 can be formed into a field plate structure by being extended over an interlayer insulating film (not shown) between the source and drain. However, there is no need to form a field plate structure between the drain electrode 12, which is disposed at the outermost end, and the p-type well region 3. This is so that the electric field strength in this place is increased, and the parasitic transistor 15 is switched to an on-state quickly, when a surge is applied.

(26) FIG. 4 is a current (Id)-voltage (Vd) characteristic diagram for the output stage MOSFET 101. For reference purposes, a current (Id)-voltage (Vd) characteristic diagram for a conventional output stage MOSFET 501 is also shown. Id is the drain current of the output stage MOSFET 101, while Vd is the drain voltage of the output stage MOSFET 101. Id also indicates a surge current flowing through the output stage MOSFET 101 and the collector current of the parasitic transistor 15. Also, Vd also indicates a surge voltage applied to the output stage MOSFET 101 and a surge voltage applied to the parasitic transistor 15.

(27) When a surge such as an ESD is applied to the drain electrode wiring 12 of the output stage MOSFET 101, avalanche occurs at the p-n junction A between the n-type collector region (n-type well region 2) and p-type base region (p-type well region 3) of the parasitic transistor 15. Of the avalanche current, the hole current forms a base current of the parasitic transistor 15, and the potential of the p-type base region (p-type well region 3) rises because of the base current and a base resistance (a lateral resistance R of the p-type base region). Owing to the p-type base region potential rising, electrons are injected from the n-type emitter region (n.sup.+ region 8) into the p-type base region (p-type well region 3), and the parasitic transistor 15 is turned on (snap-back). Owing to the snap-back of the parasitic transistor 15, the operating resistance of the parasitic transistor 15 takes on a low state, thus protecting the output stage MOSFET 101 and the integrated circuit 102, which is the internal circuit, from surge.

(28) When the p-type well region 3 and p-type well region 4 are formed simultaneously, the n.sup.+ region 8 and n-type source region 6 are formed simultaneously, and the impurity concentrations (doses) and diffusion depths thereof are the same, as previously described, increasing a width W of the n.sup.+ region 8 (n-type emitter region) increases the lateral resistance R (base resistance) of the p-type well region 3 (p-type base region) directly below the n.sup.+ region 8, and it becomes easier for the parasitic transistor 15 to operate. As a result of this, it is possible to improve the surge protection function.

(29) Also, when the width W of the n.sup.+ region 8 is greater than a width T of the n-type source region 6, the lateral resistance R of the p-type well region 3 directly below the n.sup.+ region 8 is higher than a lateral resistance R1 of the p-type well region 4 directly below the n-type source region 6. Because of this, the parasitic transistor 15 is turned on before a parasitic transistor 15a formed in the cell 4a, and the role of the surge protection element 16 can be reliably fulfilled.

(30) Also, when a value wherein the width W of the n.sup.+ region 8 and a width Q of the p.sup.+ region 9 are added together is constant, it is preferable that the width W of the n.sup.+ region 8 is in the region of one to five times the width Q of the p.sup.+ region 9.

(31) The reason for this is that the surge protection function depreciates when the width W of the n.sup.+ region 8 is in the region less than one time the width Q of the p.sup.+ region 9. Meanwhile, when the width W of the n.sup.+ region 8 is greater than five times the width Q of the p.sup.+ region 9, the width Q of the p.sup.+ region 9 becomes correspondingly smaller, the surge current density increases, and damage occurs.

(32) Also, when setting the impurity concentration of the p-type base region (p-type well region 4) to be low, the lateral resistance R of the p-type base region increases, and it becomes still easier for the parasitic transistor 15 to operate. As a result of this, it is possible to further improve the surge protection function.

(33) Also, as the one surge protection element 16 is formed on the guard ring 17 in an outer peripheral portion of the output stage MOSFET 101, there is less likely to be an effect of manufacturing variation in comparison with a surge protection element 66 of a conventional semiconductor device 500 of FIG. 7. This is because, as the area occupied by the parasitic transistor 15 is small in comparison with the area occupied by the parasitic diode 65, the in-plane variation in diffusion concentration and diffusion depth decreases.

WORKING EXAMPLE 2

(34) FIG. 5 is a main portion plan view of a semiconductor device 200 according to a second working example of the invention. Differences from the semiconductor device 100 of the first working example are that the p.sup.+ region 9 is formed in insular form, and that the n.sup.+ region 8 configuring the parasitic transistor 15 is partially widened.

(35) By the planar form of the p.sup.+ region 9 being an insular form, the planar form of the n.sup.+ region 8 being a comb tooth form (irregular form), and the n.sup.+ region 8 extending into gaps in the p.sup.+ region 9, the area of the n-type emitter region (n.sup.+ region 8) increases, and the path of a lateral current flowing through the p-type well region 3 directly below the n-type emitter region lengthens. As a result of this, the lateral resistance R of the p-type base region (p-type well region 3) increases, and it becomes easier for the parasitic transistor 15 to operate. As a result of this, it is possible to improve the surge protection function.

WORKING EXAMPLE 3

(36) FIG. 6 is a main portion sectional view of a semiconductor device 300 according to a third working example of the invention. A difference from the semiconductor device 100 of the first working example is that one portion of the p-type base region (p-type well region 3) below the n.sup.+ region 8 and p.sup.+ region 9 is formed to be shallow. By one portion of the p-type base region directly below the n-type emitter region (n.sup.+ region 8) being formed to be shallow, the lateral resistance R of the p-type base region (p.sup.+ region 9) increases, and it becomes easier for the parasitic transistor 15 to operate. As a result of this, it is possible to improve the surge protection function.

(37) Some Advantages of Embodiments of the invention include the following. 1) By forming the parasitic transistor 15 on the guard ring 17, and adopting the parasitic transistor 15 as the surge protection element 16, it is possible to provide the compact semiconductor devices 100 to 300 having the surge protection element 16.

(38) 2) By adopting the parasitic transistor 15 as the surge protection element 16, it is possible to reduce the operating resistance in comparison with when using the parasitic diode 65 as the surge protection element 66, and thus possible to improve the surge protection function.

(39) 3) By providing one surge protection element 16 on the guard ring 17, rather than providing a surge protection element 16 in each cell 4a, it is possible to make it difficult for the surge protection function to be affected by manufacturing variation (in-plane variation).

(40) 4) As the surge protection element 16 is formed on the guard ring 17, the characteristics (breakdown voltage, on-state voltage) of the output stage MOSFET 101 are not affected.

(41) In each working example, the n-type drain region 5 may be replaced with a p-type collector region, and the lateral MOSFET changed to a lateral insulated gate bipolar transistor (IGBT).

(42) Also, although an explicit description is omitted, Working Examples 1 to 3 may be combined, as would be understood by one of skill in the art, as instructed by the present disclosure. As such, examples of specific embodiments are illustrated in the accompanying drawings. While the invention is described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the invention to the described embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. In the above description, specific details are set forth in order to provide a thorough understanding of embodiments of the invention. Embodiments of the invention may be practiced without some or all of these specific details. Further, portions of different embodiments and/or drawings can be combined, as would be understood by one of skill in the art.

(43) This application is based on, and claims priority to, Japanese Patent Application No. 2012-177003, filed on Aug. 9, 2012. The disclosure of the priority application, in its entirety, including the drawings, claims, and the specification thereof, is incorporated herein by reference.