WAFER BOW REDUCTION
20170323790 · 2017-11-09
Inventors
Cpc classification
H01L21/02694
ELECTRICITY
H01L29/0834
ELECTRICITY
H01L21/0262
ELECTRICITY
H01L29/66068
ELECTRICITY
International classification
H01L21/02
ELECTRICITY
Abstract
We describe a method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide layer grown on the silicon wafer. The method includes applying nitrogen atoms during the growth process of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.
Claims
1. A method for reducing bow in a composite wafer comprising a silicon wafer and a silicon carbide epitaxial layer grown on the silicon wafer, the method comprising: applying nitrogen atoms during the epitaxial growth of the silicon carbide layer on the silicon wafer so as to generate a compressive stress within the composite wafer.
2. A method for manufacturing a composite wafer, the method comprising: forming a silicon wafer; thermally growing a silicon carbide epitaxial layer on the silicon wafer to form the composite wafer; and applying nitrogen atoms during the thermal epitaxial growth of the silicon carbide layer so as to generate a compressive stress within the composite wafer.
3. A method according to claim 1, wherein the nitrogen atoms are applied during the single crystal epitaxial growth phase of the silicon carbide layer.
4. A method according to claim 1, wherein the application of the nitrogen atoms generates the compressive stress to countermand a natural tensile stress causing the bow of the composite wafer, and optionally the compressive stress is generated at the same place within the composite wafer where the natural tensile stress is generated.
5. (canceled)
6. A method according to claim 1, wherein the interface between the silicon wafer and the silicon carbide layer includes dislocations or crystal defects, and optionally wherein the dislocations or crystal defects at the interface incorporates the nitrogen atoms at a higher rate than a single crystal.
7. (canceled)
8. A method according to claim 1, wherein the silicon carbide layer is a 3-step cubic silicon carbide (3C—SiC); and/or wherein the application of nitrogen atoms causes the substantially central part of the composite wafer to be substantially flattened so as to reduce the bow of the composite wafer; and/or wherein the nitrogen atoms are applied across substantially the whole area of the composite wafer; and/or wherein the nitrogen atoms applied during the single crystal epitaxial growth of the silicon carbide layer do not form part of the doping concentration of the silicon carbide layer.
9. (canceled)
10. (canceled)
11. (canceled)
12. A method according to claim 1, wherein the composite wafer is an on-axis wafer; or wherein the composite wafer is an off-axis wafer.
13. (canceled)
14. A silicon carbide semiconductor structure comprising: a monocrystalline silicon wafer; a silicon carbide epitaxial layer grown on the monocrystalline silicon wafer; wherein the interface between the silicon wafer and the silicon carbide layer comprises nitrogen atoms which are applied during the epitaxial growth process of the silicon carbide layer so as to generate a compressive stress within the semiconductor structure.
15. A semiconductor structure according to claim 14, wherein the nitrogen atoms are applied during the single crystal epitaxial growth phase of the silicon carbide layer.
16. A semiconductor structure according to claim 14, wherein the application of the nitrogen atoms generates the compressive stress to countermand a natural tensile stress causing the bow of the semiconductor structure, and optionally wherein the compressive stress is generated at the same place within the semiconductor where the natural tensile stress is generated.
17. (canceled)
18. A semiconductor structure according to claim 14, wherein the interface between the silicon wafer and the silicon carbide layer includes dislocations or crystal defects, and optionally wherein the dislocations or crystal defects at the interface incorporates the nitrogen atoms at a higher rate than a single crystal.
19. (canceled)
20. A semiconductor structure according to claim 14, wherein the silicon carbide layer is a 3-step cubic silicon carbide (3C—SiC).
21. A semiconductor structure according to claim 14, wherein the application of nitrogen atoms causes the substantially central part of the semiconductor structure to be substantially flattened so as to reduce bow of the semiconductor structure; and/or wherein the nitrogen atoms are applied across the substantially the whole area of the semiconductor structure; and/or wherein the nitrogen atoms applied during the crystal growth of the silicon carbide layer do not form part of the doping concentration of the silicon carbide layer.
22. (canceled)
23. (canceled)
24. A semiconductor structure according to claim 14, wherein the silicon wafer is an on-axis wafer or wherein the silicon wafer is an off-axis wafer.
25. (canceled)
26. A SiC device comprising: the semiconductor structure according to claim 14; and one or more semiconductor device or transistor structures over the semiconductor structure.
27. A SiC diode incorporating the SiC device of claim 26.
28. A SiC insulated gate bipolar transistor (IGBT) incorporating the SiC device of claim 26.
29. A SiC MOSFET incorporating the SiC device of claim 26.
30. (canceled)
31. (canceled)
32. A method according to claim 1, wherein the nitrogen atom incorporation rate is inversely proportional to the epitaxial growth rate.
33. A semiconductor structure according to claim 14, wherein the nitrogen atom incorporation rate is inversely proportional to the epitaxial growth rate.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.
[0036]
[0037]
[0038]
[0039]
[0040]
[0041]
[0042]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0043] Before describing embodiments of the present invention, a silicon carbide/silicon heteroepitaxy process will be described with reference to
[0044]
[0045] The silicon wafer 1 is placed in a silicon carbide epitaxial reactor (not shown) and is heated to about 1350° C. As shown (in highly schematic form) in
[0046] Referring to
[0047] In addition, as shown in
[0048] The present invention seeks to address this problem.
[0049]
[0050] In the present invention, the technique applied to reduce the wafer bow is very simple, which includes introducing Nitrogen (an n-type dopant in SiC) during crystal growth to develop a compressive stress. This is because Nitrogen substitutes for Carbon in the crystal lattice, but is smaller, and hence produces a compressive stress. It will be appreciated that the present technique includes applying Nitrogen atoms during the crystal growth process of 3C—SiC in addition to those introduced to provide a doping profile in the 3C—SiC. The Nitrogen atoms are introduced to generate a compressive stress within the 3C—SiC layer and the composite wafer, which can countermand the tensile stress generated within the wafer. This technique is a separate step from introducing Nitrogen for creating a doping profile.
[0051] In embodiments, the nature of the interface assists in this process in that there is a high concentration of crystal defects at the Si/SiC interface and these defects incorporate Nitrogen at a much higher rate than normal single crystal.
[0052]
[0053]
[0054]
[0055] Although in
[0056]
[0057] As can be seen, the nitrogen atom incorporation rate is inversely proportional to the growth rate, i.e. higher nitrogen atom incorporation is conducted when epitaxial growth rate is slower (e.g. about 8 micron). This is why it is advantageous (and cheaper) to grow the bulk of the layer where we want a low doping (drift region) as fast as possible.
[0058] Returning to the numbered regions of
[0059] Although the present specification makes reference to the interface of the silicon substrate and 3C—SiC epitaxial layer, it would be appreciated that the technique may also be equally applicable to other poly types of SiC.
[0060] Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.
[0061]
[0062] As can be seen, the nitrogen atom incorporation rate is inversely proportional to the growth rate, i.e. higher nitrogen atom incorporation is conducted when epitaxial growth rate is slower (e.g. about 8 micron). This is why it is advantageous (and cheaper) to grow the bulk of the layer where we want a low doping (drift region) as fast as possible.
[0063] Returning to the numbered regions of