Abstract
An integrated circuit chip having an anti-moisture-absorption film at the edge thereof and a method of forming the anti-moisture-absorption film are provided. In the integrated circuit chip which has predetermined devices inside and whose uppermost layer is covered with a passivation film, a trench is formed by etching interlayer dielectric films to a predetermined depth along the perimeter of the integrated circuit chip to be adjacent to the edge of the integrated circuit chip and an anti-moisture-absorption film is formed to fill the trench or is formed on the sidewall of the trench to a predetermined thickness, in order to prevent moisture from seeping into the edge of the integrated circuit chip. Moisture is effectively prevented from seeping into the edge of the chip by forming the anti-moisture-absorption film at the edge of the chip using the conventional processes of manufacturing the integrated circuit chip without an additional process.
Claims
1. An integrated circuit device, comprising: an integrated circuit chip; a plurality of devices formed in the integrated circuit chip; a scribe line formed at and defining the perimeter of the integrated circuit chip, said scribe line being used in separating the integrated circuit chip from other integrated circuit chips; a passivation film formed on the integrated circuit chip; a trench at a predetermined depth along the perimeter of the integrated circuit chip adjacent to the edge of the integrated circuit chip, the trench being formed at the scribe line at the perimeter of the integrated circuit chip, the predetermined depth being such that a boundary between multiple .[.layers.]. .Iadd.interlayer dielectric films .Iaddend.of the integrated circuit device intersects a sidewall of the trench; .[.and.]. .Iadd.an etching stop film formed under at least one of said multiple interlayer dielectric films, such that the bottom of said trench corresponding to said predetermined depth is formed within said one of said multiple interlayer dielectric films; and .Iaddend. an anti-moisture-absorption film in the trench at a predetermined thickness, said anti-moisture-absorption film covering the boundary between the multiple .[.layers.]. .Iadd.interlayer dielectric films .Iaddend.such that moisture is prevented from seeping into the edge of the integrated circuit chip.
2. The integrated circuit device of claim 1, wherein the anti-moisture-absorption film is formed on the sidewall of the trench.
3. The integrated circuit device of claim 1, wherein the trench is etched into at least one interlayer dielectric film of the integrated circuit chip.
4. The integrated circuit device of claim .[.1.]. .Iadd.9.Iaddend., wherein the anti-moisture-absorption film is formed by extending the passivation film at least to a sidewall of the trench.
5. The integrated circuit device of claim 1, wherein the anti-moisture-absorption film comprises a conductive layer pattern which fills the trench to a predetermined thickness and a passivation film extended so as to cover the conductive layer pattern.
6. The integrated circuit device of claim 5, wherein the conductive pattern is formed of the same material as an uppermost interconnection layer of the integrated circuit chip.
7. The integrated circuit device of claim 1, wherein the anti-moisture-absorption film comprises a conductive layer pattern which is formed on the sidewall of the trench to a predetermined thickness and a passivation film extended so as to cover the conductive layer pattern.
.Iadd.8. The integrated circuit device of claim 1, wherein the anti-moisture absorption film comprises a conductive anti-moisture absorption film..Iaddend.
.Iadd.9. The integrated circuit device of claim 1, wherein the anti-moisture absorption film comprises an insulative anti-moisture absorption film..Iaddend.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings in which like reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale emphasis instead being placed upon illustrating the principles of the invention.
(2) FIG. 1 is a plan view showing part of the surface of a wafer on which a plurality of integrated circuit chips are formed.
(3) FIG. 2 is an enlarged sectional view taken along the line 2—2 of FIG. 1.
(4) FIGS. 3A through 3F are sectional views showing processes of forming an anti-moisture-absorption film at the edge of an integrated circuit chip according to an embodiment of the present invention and the structure of the chip edge formed thereby.
(5) FIGS. 4A through 4C are sectional views showing a structure in which an anti-moisture-absorption film is formed at the edge of an integrated circuit chip according to another embodiment of the present invention.
(6) FIGS. 5A through 5F are sectional views showing processes of forming an anti-moisture-absorption film at the edge of an integrated circuit chip according to still another embodiment of the present invention and the structure of the chip edge formed thereby.
(7) FIGS. 6A through 6C are sectional views showing a structure in which the anti-moisture-absorption film is formed at the edge of the integrated circuit chip according to still another embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
(8) The present invention now will be described more fully with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. In the drawings, it will also be understood that when a layer is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Also, each of interlayer dielectric films is described to have a single-layered structure, however, can have a structure where multi-layered interlayer dielectric films are stacked. The thickness or length of layers are exaggerated for clarity.
(9) FIGS. 3A through 3F are sectional views showing processes of forming an anti-moisture-absorption film at the edge of an integrated circuit chip according to an embodiment of the present invention and the structure of the chip edge formed thereby. Chip areas and scribe lines of only one side are shown in FIGS. 3A through 3F unlike in FIG. 2. The chip areas and the scribe lines of only one side are shown in other embodiments.
(10) Referring to FIG. 3A, a trench is formed at the boundary between a chip and a scribe line. Material layer patterns 110 which form a predetermined device are formed in the chip on a substrate or an interlayer dielectric film 100. Predetermined material layer patterns 112 can be simultaneously formed in the scribe line for a test element group (TEG). Here, since the characteristic part of the present invention is the boundary between the chip and the scribe line, a detailed description of a device or material layer patterns formed inside the chip and in the center of the scribe line excluding the boundary will be omitted. In the case of a memory device, the respective memory cells and a peripheral circuit for driving the respective memory cells are generally formed inside the chip.
(11) After forming an interlayer dielectric film 120, a lower interconnection layer 130 of the chip is formed. The lower interconnection layer 130 is formed by depositing a conductive material, for example, a metal such as tungsten or aluminum, on the entire surface of the interlayer dielectric film 120 (a barrier metal layer may be included under a metal layer when the metal is used) and patterning the metal in a desired interconnection pattern.
(12) A contact hole 150 is formed by depositing an interlayer dielectric film 140 such as a silicon oxide film on the entire surface of the resultant on the lower interconnection layer 130 to a thickness of between 5,000 and 10,000 Å and by etching the interlayer dielectric film 140 in a portion where a contact is to be formed. A trench 152 is simultaneously formed at the boundary between the chip and the scribe line. To be specific, the contact hole 150 which exposes the lower interconnection layer 130 is formed in the chip, and the trench 152 is formed at the boundary between the chip and the scribe line at the same time by forming a photoresist pattern (not shown) which exposes the portions of the interlayer dielectric film 140 to be etched and plasma etching the interlayer dielectric film 140 formed of the silicon oxide using CF.sub.4 having a flow rate of between 35 and 50 sccm and CHF.sub.3 having a flow rate of between 35 and 50 sccm as etching gases, and flowing Ar having a flow rate of between 300 and 450 sccm, at a pressure of between 300 and 500 mTorr, and at an RF power of between 1,100 and 1,400 W, for between 100 and 150 seconds. The width of the trench 152 is about several μm.
(13) A conductive material layer 160 which fills the contact hole 150 is formed and the conductive material layer 160 is also formed in the trench 152, as shown in FIG. 3B, when the conductive material, for example, a metal such as tungsten or aluminum, is deposited on the entire surface of the resultant of FIG. 3A to a thickness of between 6,500 and 10,000 Å in order to form an upper interconnection layer on the entire surface of the resultant structure.
(14) Referring to FIG. 3C, the conductive material layer 160 is patterned. As a result, an upper interconnection layer 164 including a contact is formed in the chip and the conductive material is completely removed inside and around the trench 152. At this time, an interconnection pattern 162 can be formed in the scribe line, if necessary.
(15) Referring to FIG. 3D, a passivation film 170 used as the anti-moisture-absorption film is formed on the uppermost layer of the chip and the sidewall of the trench 152. The interlayer dielectric film 120 is exposed in the center of the bottom of the trench 152, since part of the passivation film 170 is removed.
(16) In order to form the structure shown in FIG. 3D, a moisture-proof film such as a silicon nitride film, a silicon oxide film which is not doped with impurities or is doped with a low concentration of impurities, or a compound film of the above films is formed on the entire surface of the resultant structure of FIG. 3C. In the present embodiment, the silicon oxide film which is not doped with impurities is deposited to a thickness of between 1,000 and 2,000 Å. The silicon nitride film is deposited on the silicon oxide film to a thickness of between 5,000 and 10,000 Å. As a result, an interface between the interlayer dielectric films 120 and 140, which is exposed on the sidewall of the trench 152 and can be a moisture-absorption path, is covered with the passivation film 170. Accordingly, the moisture-absorption path is blocked by the passivation film 170.
(17) A chip edge structure is completed by removing part of the passivation film 170, thus exposing the interlayer dielectric film 120 so that mechanical shock is not transmitted through the passivation film 170 when the wafer is sawed along the center of the scribe line. The interlayer dielectric film 120 is exposed at the bottom of the trench 152 in a process of exposing the upper interconnection layer 164 by etching the passivation film 170 in order to form a bonding pad (not shown) for wire bonding, so that an additional process is not needed. The interlayer dielectric film 120 is exposed in the center of the trench 152 and the bonding pad (not shown) in which the upper interconnection layer 164 is exposed is formed in a predetermined position of the chip by performing a photolithography process. To be specific, a photoresist pattern (not shown) is formed to expose a portion in which the bonding pad is to be formed and the center of the trench 152, and the passivation film 170 formed by stacking the silicon oxide film and the silicon nitride film is plasma etched using CF.sub.4 having a flow rate of between 65 and 90 sccm and O.sub.2 having a flow rate of between 10 and 25 sccm as etching gases, and flowing Ar having a flow rate of between 80 and 110 sccm, at a pressure of between 300 and 500 mTorr, and at an RF power of between 1,000 and 1,300 W, for between 60 and 95 seconds.
(18) When the reliability of the integrated circuit chip is tested at a high temperature, a high humidity, and a high pressure in the state that the anti-moisture-absorption film is formed of the passivation film 170 on the sidewall of the trench 152, moisture is prevented from seeping into the sidewall of the trench formed at the boundary between the chip and the scribe line, unlike in the conventional technology. Accordingly, reliable integrated circuit chips are obtained.
(19) When the chips are sawed along the center of the scribe lines after the reliability of the integrated circuit chips tested, the right side of a dotted line 200 is cut and removed and the chip on the left side of the dotted line 200 is divided into separate chips.
(20) FIG. 3E is a modification of the present embodiment. The position where part of a passivation film 172 is removed in FIG. 3E is different from the position where part of the passivation film 170 is removed in FIG. 3D. Meanwhile it is probable that a small amount of moisture will seep into the interface between the interlayer dielectric film 120 exposed to the bottom of the trench 152 and the passivation film 170 in the structure shown in FIG. 3D. However, the seeping of moisture is completely prevented in the structure shown in FIG. 3E.
(21) FIG. 3F is another modification of the present invention, in which a passivation film 174 fills a trench 154. Here, the width of the trench 154 is formed to be equal to or less than twice the thickness of the passivation film 174 so that the passivation film 174 fills the trench 154. In the structure shown in FIG. 3F, it is possible to completely prevent the seeping of moisture like in the structure shown in FIG. 3E.
(22) FIGS. 4A through 4C are sectional views showing the structure of the edge of a chip according to another embodiment of the present invention. Conductive material patterns 166, 167, and 168 which are formed of the same material as the upper interconnection layer 164 in the chip are left inside the trench or on the sidewall of the trench in the present embodiment, unlike in the embodiment described above in connection with FIGS. 3A through 3F.
(23) In order to form the structure shown in FIG. 4A, in the step corresponding to FIG. 3C of the embodiment of FIGS. 3A through 3F, the conductive material is not completely removed inside and around the trench 156 when the upper interconnection layer 164 is formed and is left on the sidewall of the trench 156. The structure shown in FIG. 4A is obtained through the same process as the embodiment of FIGS. 3A through 3F described with reference to FIG. 3D. The width of the trench 156 is made wider than the width of the trench 152 shown in FIG. 3A, considering the thickness of the conductive material pattern 166 left on the sidewall of the trench 156.
(24) The edge of the chip having the structure shown in FIG. 4B is a modification of the present embodiment, in which the conductive material pattern 167 is left on the sidewall and the bottom of the trench 156. The part of the passivation film 172 is removed in a portion on the scribe line side adjacent to the trench 156.
(25) The structure shown in FIG. 4C is another modification of the present embodiment, in which the conductive material pattern 168 fills the trench 154. In order to form the edge of the chip having the structure shown in FIG. 4C, after the width of the trench 154 is formed to be equal to or less than twice the thickness of the conductive material layer 168 so that the conductive material layer 168 fills the trench 154, the conductive material layer 168 which fills the trench 154 is left when the upper interconnection layer 164 of the chip is formed, like in the structure shown in FIG. 3F of the embodiment of FIGS. 3A through 3F.
(26) In FIGS. 4A through 4C, the upper interconnection layer 164 is described as being separated from the conductive material patterns 166, 167, and 168 left on the sidewalls of the trench 156 or inside the trench 154. However, the upper interconnection layer 164 does not need to be separated from the conductive material patterns 166, 167, and 168 unless there is an electrical influence such that the conductive material patterns 166, 167, and 168 on the sidewalls of the trenches or inside the trenches are connected to other elements. This is true of the embodiment of FIGS. 6A through 6C described below in detail.
(27) In the present embodiment, it is possible to prevent moisture from seeping into the edge of the chip since the interface between the interlayer dielectric films 120 and 140 which becomes the moisture-absorption path is not exposed.
(28) FIGS. 5A through 5F are sectional views showing processes of forming the anti-moisture-absorption film at the edge of the chip according to a third embodiment of the present invention and the structure of the chip edge formed thereby. The third embodiment is different from the first embodiment of FIGS. 3A through 3F only in that an etching stop film is formed with a predetermined material layer 190 which forms a device in the chip under the lower interconnection layer 130, so as to easily control the depth to which the interlayer dielectric films 140 and 122 are etched in order to form the trench 152.
(29) Referring to FIG. 5A, the material layer patterns 110 which form a predetermined device are formed on the substrate or the interlayer dielectric film 100 and the interlayer dielectric film 120 is formed on the material layer pattern 110, like in FIG. 3A. The predetermined material layer 190 which forms the device in the chip is formed on the interlayer dielectric film 120 to be extended to the scribe line. The material layer 190 can be formed of polycrystalline silicon which is doped with impurities, which forms the upper electrode of a memory cell capacitor when the device formed in the chip is a DRAM device. The material layer 190 can be formed of other interconnections and a material having etching selectivity with respect to the interlayer dielectric films 122 and 140 which is generally formed of the silicon oxide thereon. It is not necessary that the material layer 190 must be formed of the conductive material.
(30) After forming the lower interconnection layer 130 by interposing the interlayer dielectric film 122 on the material layer 190 which will become the etching stop film and forming the interlayer dielectric film 140 on the lower interconnection layer 130, the trench 152 is formed together with the contact hole 150 of the chip and at the boundary between the chip and the scribe line as described in FIG. 3A. The contact hole 150 and the trench 152 are etched to have different depths, however, they can be simultaneously formed by etching until both the lower interconnection layer 130 and the etching stop film 190 are exposed. Therefore, it is possible to etch the trench 152 to a uniform depth.
(31) As shown in FIG. 5B, the conductive material layer 160 is formed by depositing the conductive material which will form the upper interconnection layer of the chip on the entire surface of the resultant of FIG. 5A.
(32) As shown in FIG. 5C, a predetermined interconnection pattern 162 in the scribe line and in the upper interconnection layer 164 of the chip are formed by patterning the conductive material layer 160, and the conductive material is completely removed inside and around the trench 152. Also, the material layer 190 exposed by removing the conductive material in the trench 152 is removed. Here, the conductive material layer 160 and the material layer 190 exposed at the bottom of the trench 152 can be removed by two-step etching using an etching gas or an etching solution. However, it is convenient to remove the conductive material layer 160 and the material layer 190 used as the etching stop film by successively etching the conductive material layer 160 and the material layer 190 using an etching gas or etching solution having low etching selectivity with respect to the two materials which form the conductive material layer 160 and the material layer 190. Namely, when the conductive material layer 160 and the material layer 190 are formed of aluminum and polycrystalline silicon, respectively, polycrystalline silicon reacts with aluminum due to heat generated when aluminum is deposited and reflown, thus being metalized (it is possible to observe by a scanning electron microscope that polycrystalline silicon is metalized). Therefore, metalized polycrystalline silicon is removed by plasma etching aluminum using BCl.sub.3 having a flow rate of between 35 and 60 sccm and Cl.sub.2 having a flow rate of between 30 and 50 sccm as etching gases, and flowing N.sub.2 having a flow rate of between 10 and 25 sccm, and at a pressure of between 100 and 250 mTorr, an RF power of between 300 and 700 W, for between 100 and 160 seconds.
(33) Meanwhile, the exposed material layer 190 which was used as the etching stop film may not be removed, so that it remains on the bottom of the trench 152, unless there is an influence to other elements, as in the embodiment of FIGS. 6A through 6C described below in detail.
(34) The structure shown in FIG. 5D is obtained through the process described with reference to FIG. 3D.
(35) The edge of the chip and the anti-moisture-absorption film having the structures shown in FIGS. 5E and 5F are modifications of the present embodiment. A description of the modifications will be omitted since the modifications are different from the modifications described with reference to FIGS. 3E and 3F only in that the material layer 190 used as the etching stop film (which is etched later and comes to have the form denoted by reference numeral 192) is used.
(36) According to the present embodiment, it is possible to prevent moisture from seeping into the edge of the chip since the anti-moisture-absorption film is formed at the edge of the chip and to easily control the depth to which the trench is etched in the process of forming the anti-moisture-absorption film.
(37) FIGS. 6A through 6C are sectional views showing the structures of the edge of the chip and the anti-moisture-absorption film according to a fourth embodiment of the present invention. The structure of the present embodiment is obtained by combining the structure of the second embodiment of FIGS. 4A through 4C with the structure of the third embodiment of FIGS. 5A through 5F. The etching stop film 190 is used during the etching of the trench and the conductive material patterns 166, 167, and 168 which are formed of the same material as the upper interconnection layer 164 in the chip are left inside the trenches 156 and 154. Since the method of forming the edge of the chip according to the present embodiment is obtained by combining the method of the second embodiment of FIGS. 4A through 4C with the method of the third embodiment of FIGS. 5A through 5F in which the etching stop film 190 is used, a description thereof will be omitted.
(38) As mentioned above, according to the present invention, reliable integrated circuit chips are obtained by preventing moisture from seeping into the edges of the chips when the reliability of the integrated circuit chips are tested. In particular, according to the present invention, the anti-moisture-absorption film is formed at the edge of the chip using conventional process steps used in manufacturing integrated circuit chips without an additional process.
(39) While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
