METHOD FOR PRODUCING A CONDUCTIVE MULTIPLE SUBSTRATE STACK

Abstract

A method for producing a multiple-substrate stack from an, in particular wavelength-sensitive, semiconductor substrate and at least one further, in particular wavelength-sensitive, semiconductor substrate with the following steps: applying a dielectric layer, which is electrically conductive at least in certain sections, onto at least one substrate surface of at least one of the semiconductor substrates, and contacting the semiconductor substrate with the further semiconductor substrate and forming an electrically conductive connection between the semiconductor substrates.

Claims

1-13. (canceled)

14. A method for producing a multiple-substrate stack from a first wavelength-sensitive semiconductor substrate constructed as a solar cell and at least one further wavelength-sensitive semiconductor substrate constructed as a solar cell, the method comprising: applying in each case a dielectric layer, which is electrically conductive, onto contacting opposite substrate surfaces of the semiconductor substrates, and contacting the first semiconductor substrate with the at least one further semiconductor substrate at the electrically conductive dielectric layers, thereby forming an electrically conductive connection between the semiconductor substrates, wherein after or during the contacting of the semiconductor substrates, forming a permanent fusion-bond between the semiconductor substrates.

15. The method according to claim 14, in which each of the semiconductor substrates has an n-doping layer and a p-doping layer, wherein adjacent semiconductor substrates in each case abut, by way of an n-doped layer, against a p-doping layer of an adjacent semiconductor substrate.

16. The method according to claim 14, wherein the dielectric layer is constructed as a matrix composite material by means of a sol-gel process to which conductive particles are added.

17. The method according to claim 16, wherein the dielectric layer is constructed as a ceramic layer.

18. The method according to claim 16, wherein the dielectric layer is a silicon oxide layer.

19. The method according to claim 16, wherein the conductive particles are nanoparticles.

20. The method according to claim 14, wherein the dielectric layer is created by applying nanoparticles, at least in certain sections, and subsequent oxidation of the dielectric layer by means of a native oxide.

21. The method according to claim 14, wherein the semiconductor substrates are constructed in a wavelength-sensitive manner in, at least partially, different wavelength ranges.

22. The method according to claim 21, wherein the semiconductor substrates are constructed in a wavelength-sensitive manner in completely different wavelength ranges.

23. The method according to claim 14, wherein a mechanical alignment of the semiconductor substrates takes place before or during the contacting without optical means and/or without optical alignment markings on the semiconductor substrates.

24. The method according to claim 14, wherein the semiconductor substrates have electrically conductive passages for the electrically conductive connection of substrate surfaces of each of the semiconductor substrates, which substrate surfaces face away from one another in each case.

25. The method according to claim 24, wherein the dielectric layer is constructed only in certain sections at the passages with electrically conductive contact points.

26. The method according to claim 25, wherein the contact points are constructed with a diameter D, which is at least the same size as, an average alignment error f during contacting.

27. The method according to claim 26, wherein the diameter D is larger than the average alignment error f during contacting.

28. A multiple-substrate stack produced with a method according to claim 14, the multiple-substrate stack comprising: a first wavelength-sensitive semiconductor substrate and at least one further wavelength-sensitive semiconductor substrate, wherein a dielectric layer, which is electrically conductive at least in certain sections, is provided on at least one substrate surface of at least one of the semiconductor substrates, and an electrically conductive connection between the semiconductor substrates is produced by contacting the first semiconductor substrate with the at least one further semiconductor substrate.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0087] FIG. 1 shows a schematic view of an embodiment according to the invention of a substrate stack, comprised of three substrate layers,

[0088] FIG. 2 shows a schematic side view of an enlargement of a substrate stack according to the invention in a first embodiment according to the invention with substrates oxidized on one side,

[0089] FIG. 3 shows a schematic side view of an enlargement of a substrate stack according to the invention in a first embodiment according to the invention with substrates oxidized on two sides,

[0090] FIG. 4 shows a schematic side view of an enlargement of a substrate stack according to the invention in a second embodiment according to the invention with substrates oxidized on one side,

[0091] FIG. 5 shows a schematic side view of an enlargement of a substrate stack according to the invention in a third embodiment according to the invention with substrates oxidized on two sides,

[0092] FIG. 6 shows a schematic side view of an enlargement of a substrate stack according to the invention in a third embodiment according to the invention with substrates oxidized on one side,

[0093] FIG. 7 shows a schematic side view of an enlargement of a substrate stack according to the invention in a fourth embodiment according to the invention with substrates oxidized on two sides,

[0094] FIG. 8 shows a schematic side view of an enlargement of the preferred embodiment of a substrate stack according to the invention,

[0095] FIG. 9a shows a schematic view of a first contact point according to the invention,

[0096] FIG. 9b shows a schematic view of a second contact point according to the invention and

[0097] FIG. 9c shows a schematic view of a third contact point according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0098] FIG. 1 shows a schematic cross-sectional view of a substrate stack 1 according to the invention, comprised of three substrates 2, 2′, 2″, The stacking of more or fewer than three substrates 2, 2′, 2″ is also conceivable. The wavelength sensitivity of the substrates is symbolized by wave trains with different wavelength, which represent the electromagnetic waves, in the sense of the partial image, actually the photons. Corresponding contacts for tapping the total voltage generated by the solar cell stack on the outer side are not shown.

[0099] FIG. 2 shows an enlargement of the section A of the schematic cross-sectional view according to FIG. 1 in a first embodiment according to the invention, in which one can see dielectric layers, particularly oxide layers, 3, by means of which the substrates 2, 2′, 2″ have been connected to one another.

[0100] The dielectric layers 3 alternate in this case between the individual substrates 2, 2′, 2″. This alternation is preferably achieved in such a manner that always only the surfaces 2o, 2o′, 2o″ of the substrates 2, 2′, 2″ are oxidized and are connected to a respectively non-oxidized surface 2u, 2u′, 2u″ of a second substrate 2, 2′, 2″. The final oxidation of one of the outer substrates 2, 2′, 2″ can take place after the connection of the substrates 2, 2′, 2″ and has likewise been shown. Should for example the substrate 2″ be the last and/or lowermost substrate in the substrate stack 1, an oxidation of the surface 2u″ is conceivable, in order to fully enclose the substrate stack with oxide. An oxidation of the surface 2u″ of this type is illustrated in FIG. 2. In this specific embodiment according to the invention, passages 4 create a conductive connection between two substrates 2, 2′, 2″ in each case. The tapping of the voltage takes place at outer, exposed contact points 5, which have a diameter D.

[0101] The connection of the substrates 2, 2′, and 2″ can theoretically likewise take place by means of a direct bond. If, however, the materials of the substrates 2, 2′, 2″ are different from the materials of the dielectric layer 3, the thus-created direct bonding does not take place with optimum quality.

[0102] The production of the contact points 5 takes place with very imprecise masks and processes, wherein the average diameter D of the contact points 5 is larger than the average alignment error f between the respective adjacent contact points 5. Thus, the production of the contact points 5 on the respective substrate can also take place faster and less expensively. The ratio between the diameter D and the average alignment error f is approximately 2 in the embodiment shown.

[0103] A preferred embodiment according to the invention therefore includes oxidizing all surfaces 2o, 2o′, 2o″, 2u, 2u′, 2u″, all substrates 2, 2′, 2″ according to FIG. 3, to create an, in particular full-area, dielectric layer 3. Owing to the oxidation of both surfaces 2o, 2o′, 2o″, 2u, 2u′, 2u″ of the substrates 2, 2′, 2″, contact points 5 in the dielectric layers are simultaneously and/or subsequently created on both sides of the substrates 2, 2′, 2″. FIG. 4 shows a particular embodiment, which is interesting for the solar industry, in which no passages 4 exist. The tapping of the voltage takes place at the outer, exposed contact points 5. The individual p- and n-transitions are alternately connected to one another by means of the contact points 5 located in the bond interface. Should it be expedient to nonetheless incorporate corresponding passages 5, these can be produced according to FIGS. 2-3.

[0104] FIG. 5 shows an embodiment according to the invention of the two-sided oxidation of a substrate 2, 2′, 2″ without TSVs.

[0105] FIGS. 6 and 7 show the most preferred embodiments according to the invention. The conductive connection between the n- and p-regions of the substrates 2, 2′, 2″ is not produced by contact points 5, which have been introduced regularly or irregularly into the dielectric layers 3, but rather by a network of nanoparticles 6, which have been embedded into the dielectric layer 3′. The density of the dielectric nanoparticles 6 is so large in this case that an electrical conductive connection between the n-region of the one solar cell and the p-region of the second solar cell always results. It is also conceivable to arrange the nanoparticles 6 only in one part region of the dielectric layer 3′, at which contacting should take place.

[0106] FIG. 8 shows an enlargement of the dielectric layers V with the corresponding nanoparticles 6.

[0107] The contact points 5 located on the outer side of the substrate stack I according to the invention are preferably used for voltage tapping.

[0108] In very specific, and therefore not preferred, embodiments, it may also be possible to dispense with the oxide layers 3 completely, in order to connect the solar layers 2, 2′, 2″ to one another directly.

[0109] The FIGS. 9a-c show three contact points 5, 5′ and 5″ according to the invention. The two contact points 5 and 5″ according to the invention cover the whole area, whilst the second contact point 5′ according to the invention is constructed in a ring-shaped manner. The contact point 5′ according to the invention has the diameter D and a ring width d. Two such contact points 5′ located on substrates 2, 2′, 2″, which are opposite one another in each case, overlay one another either completely or intersect in two or one intersection point. As the complete overlaying and the contacting reduced to one point is somewhat unlikely in the case of positioning and contacting (carried out without alignment plants), two such contact points will in practice to a large extent or always intersect at two intersection points. Electricity transmission is then reduced to the two contact points. The larger is the diameter D of the contact point 5′, the less sensitively the embodiment according to the invention reacts to alignment errors, as a larger diameter D also means a greater likelihood of contacting.

REFERENCE LIST

[0110] 1, 1′ Substrate stack [0111] 2, 2′, 2″ Substrate [0112] 2o, 2o′ 2o″ Substrate surface [0113] 2u, 2u′, 2u″ Substrate surface [0114] 3, 3′ Dielectric layer [0115] 4 Passage [0116] 5, 5′, 5″ Contact point [0117] 6 Nanoparticles [0118] p p-doping layer of the semiconductor substrate [0119] n n-doping layer of the semiconductor substrate [0120] D Average diameter [0121] f Average alignment error