Improvements Relating to Electronic Memory Devices

Abstract

A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.

Claims

1. A memory cell for storing one or more bits of information, the memory cell comprising: a semiconductor substrate on which is provided a source terminal, a drain terminal and a channel extending between the source and drain terminals; and a control gate and a floating gate, the floating gate being disposed between the control gate and the channel, and the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate, in write and erase operations, to provide at least first and second occupancy states of the floating gate, the channel being arranged to provide a minimum threshold voltage to be applied between the control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.

2. The memory cell according to claim 1, wherein the memory cell has a heterojunction at the interface between the channel and the semiconductor substrate, in which the lowest energy level at which a charge carrier may reside in a conduction band of the channel has a higher energy than the valence band of the semiconductor substrate.

3. The memory cell according to claim 1, wherein the channel comprises a quantum well having discrete internal energy levels for accommodating charge carriers in the channel.

4. The memory cell according to claim 3, wherein the quantum well is defined between a charge barrier and the substrate.

5. The memory cell according to claim 1, wherein a charge barrier and the semiconductor substrate define the walls of the quantum well.

6. The memory cell according to claim 1, wherein in the absence of any applied bias across the channel the channel comprises an electric potential barrier at an interface between the channel and the charge barrier, and an electric potential barrier at an interface between the channel and the substrate, and wherein the electric potential barrier at the interface between the channel and the substrate enables the selective passage of charge carriers between the semiconductor substrate and the channel.

7. (canceled)

8. The memory cell according to claim 1, wherein the channel is formed by having offset conduction and/or valence bands to form heterojunctions at the interface between the channel and the charge barrier, and at the interface between the channel and the semiconductor substrate.

9. The memory cell according to claim 1, wherein the channel is formed by a narrow band gap semiconductor being disposed between two wide band gap semiconductors.

10. The memory cell according to claim 1, wherein the interface between the channel and the substrate is a type-III heterojunction.

11. The memory cell according to claim 1, wherein the channel is an InGaAs quantum well and one of the adjacent barrier materials is GaSb.

12. The memory cell according to claim 3, wherein one or both of: the lowest of the internal energy levels of the quantum well has a higher energy than the valence band energy of the substrate in the absence of an electric field applied across the memory cell, and the lowest of the internal energy levels of the quantum well has a higher energy than the Fermi energy of the substrate in the absence of an electric field applied across the memory cell.

13. (canceled)

14. The memory cell according to claim 6, wherein one or both of: the selective passage of charge carriers between the substrate and the channel, in use, is controllable by controlling the shape and/or magnitude of the electric potential barrier at the interface between the channel and the semiconductor substrate, and the passage of charge carriers between the substrate and the channel is controllable by the application of an electric field across the memory cell.

15. (canceled)

16. The memory cell according to claim 1414, wherein in response to the application of an electric field, the lowest confined internal state of the quantum well has a lower energy than the valence band energy of at least a portion of the substrate.

17. The memory cell according to claim 1, wherein the channel is unoccupied by charge carriers in the absence of an applied electric field.

18. The memory cell according to claim 1, wherein the channel is one or both of non-conductive and insulating in the absence of an applied electric field.

19. A memory device comprising a plurality of memory cells as claimed in claim 1, wherein the floating gate is configured to enable the selective passage of charge carriers into and out of the floating gate by resonant tunnelling, in write and erase operations.

20. The memory device as claimed in claim 19, wherein the plurality of memory cells may be arranged in an array comprising a plurality of columns and a plurality of rows, and the memory device comprises at least one first electrical contact arranged to provide a voltage to the control gate of each memory cell in a column of the array, and at least one second electrical contact arranged to provide a voltage to at least one of the source, drain or base gate terminals.

21. The memory device as claimed in claim 20, wherein the first electrical contact is configured to apply a first portion of a required voltage to a desired column within the array, and the second electrical contact is configured to apply a second portion of the required voltage to a desired row within the array, such that a target cell within the array receives the full required voltage.

22. The memory device as claimed in claim 21, wherein the required voltage is any of the read voltage, write voltage and erase voltage.

23. The memory device as claimed in claim 19, wherein either the source terminals of the plurality of memory cells or the drain terminals of the plurality of memory cells are electrically connected to a base gate terminal that is common to the plurality of memory cells.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0082] FIG. 1 is a schematic cross-sectional view of a memory cell according to the invention;

[0083] FIG. 2 is a schematic conduction band energy level diagram of a memory cell according to the invention;

[0084] FIG. 3 is a schematic conduction and valence band energy level diagram at the channel-substrate interface of a memory cell according to the invention; and

[0085] FIG. 4 is a schematic representation of an array of memory cells according to the invention.

DETAILED DESCRIPTION

[0086] FIG. 1 illustrates a schematic cross section of a memory cell according to the invention, which is generally designated 10. The memory cell 10 comprises source and drain terminals 12,14, a channel 16 between the source and drain terminals 12,14, a base gate terminal 15 at the base of the semiconductor substrate 18, and a control gate 24 for inducing a change in the conductivity of the channel 16 in the semiconductor substrate 18 between the source and drain terminals 12,14. The memory cell also comprises a floating gate 26 disposed between the control gate 24 and the semiconductor substrate 18.

[0087] The floating gate 26 is electrically isolated from the control gate 24 by a charge blocking barrier 30, and the floating gate 26 is electrically isolated from the semiconductor substrate 18, and therefore the channel 16 in the semiconductor substrate 18, by a charge trapping barrier 28. The charge trapping barrier 28 is adapted to enable the selective passage of charge carriers between the floating gate 26 and the channel 16 in the semiconductor substrate 18, in use, to modify the one or more bits of information stored by the memory cell 10. In contrast, the charge blocking barrier 30 prevents the passage of charge carriers between the control gate 24 and the floating gate 26.

[0088] The channel 16 differs from that of a conventional memory cell in that the channel 16 is formed from a different material grown onto the semiconductor substrate 18 material. The channel 16 is grown upon the semiconductor substrate 18 epitaxially, for example by molecular beam epitaxy (MBE) or any other appropriate process. The semiconductor substrate 18 is formed of gallium antimonide (GaSb) and is disposed upon a base structure 20, 22 that enables the use of lower cost materials, and may facilitate integration into silicon-based devices. In particular, the uppermost base layer 20 of the base structure 20,22 is formed of gallium arsenide (GaAs), and the semiconductor substrate 18 is disposed upon the uppermost base layer 20 using the interface-misfit method (IMF). The uppermost base layer 20 is disposed upon the lowermost base layer 22, which is formed of silicon (Si) or of germanium (Ge) on silicon.

[0089] Alternatively, the semiconductor substrate 18 may be disposed on the uppermost base layer 20 of GaAs with a greater thickness, ie with no additional lowermost base layer. This may be advantageous since GaAs is a common compound semiconductor and is widely available.

[0090] Alternatively, the semiconductor substrate 18 may be disposed on an uppermost base layer 20 of Si with a greater thickness, ie with no additional lowermost base layer. This may be advantageous since Si is the most common semiconductor and is widely available. In such an implementation it would be advantageous to mitigate the potentially detrimental effect of the lattice mismatch of the substrate 18 and the uppermost base layer 20 with, for example, the inclusion of a strain-relieving mechanism. One example of such a mechanism is the inclusion of one or more atomic monolayers provided between the substrate 18 and the uppermost base layer 20, although it will be appreciated that this may be provided by any other known suitable means. The one or more atomic monolayers may comprise AlSb. The one or more atomic monolayers may comprise 10, 15, or 20 atomic monolayers.

[0091] Alternatively, the semiconductor substrate 18 may have a greater thickness and be formed from only gallium antimonide (GaSb). The memory cell 10 may be more expensive to manufacture in this form, but does not require any lattice matching with a base structure.

[0092] The charge trapping barrier 28 is formed of alternating layers of indium arsenide (InAs) and aluminium antimonide (AlSb) to generate two narrow quantum wells (ie three resonant tunnelling barriers), and is disposed upon an upper surface of the channel 16. The layers of the charge trapping barrier 28 are substantially lattice matched and have a large conduction band offset.

[0093] The floating gate 26 is disposed on an upper surface of the charge trapping barrier 28, and is formed by indium arsenide (InAs), the thickness of which is not critical, but may typically be in the region of 10 to 50 nm. The floating gate 26 is an electrically isolated quantum well, defined between the charge trapping barrier 28 and the charge blocking barrier 30, which is suitable for retaining a finite number of charge carriers in quantised energy levels.

[0094] Situated above the floating gate 26 is the charge blocking barrier 30. The charge blocking barrier 30 may be formed by 15 nm of aluminium antimonide (AlSb). Such a charge blocking barrier 30 has a thickness that is substantially equal to the thickness of the charge trapping barrier 28. Furthermore, the charge blocking barrier 30 has an electric potential barrier that is substantially equal to the electric potential barrier of the charge trapping barrier 28. Alternatively, since the charge blocking barrier should have insulating properties and is disposed above the semiconductor layers of the device it may be formed by a dielectric layer, for example an oxide, such as silicon dioxide (SiO.sub.2) or aluminium oxide (Al.sub.2O.sub.3). Aluminium oxide is a convenient choice as aluminium is often readily available in compound semiconductor epitaxy systems such as molecular beam epitaxy and vapour phase epitaxy, so may be deposited in situ in the epitaxy reactor as a thin layer that will naturally oxidise ex situ, protecting the semiconductor layers underneath. In practice, an additional dielectric layer may be disposed ex situ so as to ensure the protection of the semiconductor layers

[0095] The control gate 24 is formed of any suitable conductive material, such as a metal, for example gold.

[0096] The charge trapping barrier 28, the floating gate 26, and the charge blocking barrier 30, may be formed on the semiconductor substrate 18, ie onto the channel 16, by any suitable method, for example by molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or chemical vapour deposition (CVD), or the like.

[0097] After growth, the cell 10 is processed using standard semiconductor lithography techniques. Contacts are made to the source 12, drain 14, control gate 24 and base gate terminal 15 for the application of voltages and to allow the passage of current through the cell 10.

[0098] As shown in FIG. 2, the charge trapping barrier 28 defines electric potential barriers, which define a series of quantum wells that enable resonant tunnelling. The quantum wells are of different sizes, and are specifically formed by layers of 1.8 nm of AlSb, 2.4 nm of InAs, 1.2 nm of AlSb, 3.0 nm of InAs, 1.8 nm of AlSb. The electric potential barriers of the charge trapping barrier 28 have resonant energies, indicated by the dotted lines in FIG. 3, which enable the passage of charge carriers at, or substantially at, those energies through the respective electric potential barrier.

[0099] The charge trapping barrier 28 is modelled to ensure that the resonant energies are not aligned when no voltage is applied to the memory cell 10, but to provide a substantial alignment of resonant energies of the electric potential barriers when a pre-determined electric field is applied across the charge trapping barrier 28, allowing charge carriers to pass from the channel 16 into the floating gate 26, or vice versa.

[0100] When the cell 10 is not being used, no voltages should be applied. In this state the large potential barrier 30 between the floating gate 26 and the control gate 24 prevents the passage of charge between them. Similarly, no charge may flow between the floating gate 26 and the channel 16 because the energies of the confined states in the two quantum wells in the charge trapping barrier 28 are high and are not coincident with each other.

[0101] In order to write to the cell 10, the drain 14 is shorted to the base gate terminal 15 contact (ground), and a voltage of about +2.5 V is applied between the control gate 24 and the source 12. This will align the lowest quantum confined states in the two quantum wells that form part of the charge trapping barrier 28, such that electrons may rapidly pass into the floating gate 26 by the process of resonant tunnelling.

[0102] In order to erase from the cell 10, the drain 14 is shorted to the base gate terminal 15 (ground), and a voltage of about −2.5 V is applied between the control gate 24 and the source 12. This will align the lowest confined states in the floating gate 26 and the adjacent quantum wells in the charge trapping barrier 28 such that electrons may rapidly pass out of the floating gate 26 by the process of resonant tunnelling into (a higher energy state of) the other quantum well in the charge trapping barrier 30 and thereafter into the channel 16.

[0103] In order to read the cell 10 without applying a significant voltage between the control gate 24 and the floating gate 26, which are in close proximity, and thereby avoiding the flow of charge between them, the source should not be shorted to the base gate terminal 15. Instead, a voltage of about +0.5 V should be applied between the control gate 24 and the base gate terminal 15, such that in the absence of charge in the floating gate 26 the carriers in the semiconductor substrate 18 will be driven into the channel 16 making it more conductive and giving a reading of ‘1’, and that in the presence of charge in the floating gate 26, the conductivity of the channel 16 will be substantially less enhanced giving a reading of ‘0’.

[0104] This is generally in line with the operation of conventional flash memory. However, unlike conventional flash memory, in the memory cell 10 according to the present invention, the channel 16 in the semiconductor substrate 18 comprises a quantum well that is naturally non-conductive. This is illustrated in greater detail in FIG. 3.

[0105] In FIG. 3, it can be seen that the channel 16 comprises a quantum well defined by the electric potential barriers of the adjacent semiconductor substrate 18 and the adjacent charge trapping barrier 28. The electric potential barrier of the adjacent semiconductor substrate 18 is the conduction band 40 of the semiconductor substrate 18. The quantum well is particularly narrow, eg 15 nm, such that quantum effects dictate that the quantum well has quantized energy levels, otherwise known as confined energy levels, the lowest of which (ie the ground state energy level) is indicated by the dotted line 42. These confined energy levels represent the energy levels charge carriers must occupy whilst in the quantum well.

[0106] At a zero applied bias, it can be seen that the valence band 44 of the semiconductor substrate 18 has a lower energy than the quantized energy state 42 of the channel 16. Thus, in normal conditions, charge carriers will not move from the semiconductor substrate 18 into the channel 16, resulting in the channel 16 being unoccupied, ie insulating or non-conductive.

[0107] However, by applying a bias of, for example, 0.3V, between the control gate 24 and the base gate terminal 15, it can be seen that the valence band energy 46 of the semiconductor substrate 18 is shifted. The valence band energy 46 is shifted such that a portion of the valence band 46 is raised enough to exceed the ground-state energy level 42 of the quantum well.

[0108] In response to the applied bias, since a portion of the valence band 46 exceeds the ground-state energy 42 of the quantum well, the charge carriers in the valence band 46 move into the quantum well, ie the channel 16 becomes occupied, and therefore conducting.

[0109] The memory cell 10 has a write voltage that, when applied between the control gate 24 and the source 12, causes flow of electrons into the channel 16, and then from the channel 16, through the charge trapping barrier 28, into the floating gate 26. The electrons move through the charge trapping barrier 28 in a conventional manner, ie by resonant tunnelling, in order to write to the floating gate 26. The number of electrons retained within the floating gate 26 when the electric field is removed may be dependent on the form of the floating gate 26. The memory cell 10 also has an erase voltage that, when applied between the control gate 24 and the source 12, causes flow of electrons from the floating gate 26, through the charge trapping barrier 28, into the channel 16, and then out of the channel 16 back into the semiconductor substrate 18. Similarly, the electrons move the opposite way through the charge trapping barrier 28 in a conventional manner, ie by resonant tunnelling, in order to erase from the floating gate 26. During storage, the electrons are retained in the floating gate 26, and no bias needs to be applied on the control gate 24, in order for the memory cell to store the one or more bits of information provided by the presence or otherwise of electrons in the floating gate 26.

[0110] In response to a lesser applied bias, the valence band energy of the semiconductor substrate 18 would be shifted less, ie not enough for a portion to exceed the ground-state energy level 42 of the quantum well, and the channel 16 would remain insulating. In response to a greater applied bias, the valence band would be shifted more, ie enough for a larger portion of the valence band to be raised enough to exceed the ground-state energy level 42 of the quantum well. It will therefore be understood that the density of charge carriers in the channel 16, and hence the conductivity of the channel 16, depends on the bias applied between the control gate and the base gate terminal.

[0111] There is therefore a threshold voltage which, when applied between the control gate 24 and the base terminal gate 15 or between the control gate 24 and the source terminal 12, raises the valence band of the adjacent semiconductor substrate material 18 just enough to exceed the ground-state energy 42 of the quantum well, and thus transition the channel 16 between an insulating state and a conducting state.

The threshold voltage (V.sub.th) of the memory cell 10 may therefore be defined as the value of the control gate-source voltage, or the control gate-base gate terminal voltage, when the conductivity of the conducting channel connecting the source 12 and drain 14 of the memory cell 10 switches between a depleted state, ie depleted of charge and therefore insulating and only allowing inherent leakage current, and a conducting state. The memory cell 10 is arranged to provide a change to the threshold voltage when one or more charge carriers, eg electrons, are retained by the floating gate 26.

[0112] The memory cell 10 achieves a State “0” when there are charge carriers stored in the floating gate 26, and a State “1” when there are less charge carriers, or no charge carriers, stored in the floating gate 26. In order to read the state of the memory cell 10, a read voltage (V.sub.read) is applied to the control gate 24, the read voltage (V.sub.read) being between the first threshold voltage (V.sub.th) of the memory cell 10 in State “0”, and the second, lower, threshold voltage (V.sub.th) of the memory cell 10 in State “1”. The applied read voltage (V.sub.read) results in a first current at the source 12 and/or drain 14 when the memory cell 10 is in State “1”, and no or negligible current when the memory cell 10 is in State “0”. The device into which the memory cell is incorporated therefore includes an arrangement for sensing or measuring the current flow between the source and the drain of the memory cell.

[0113] Although the memory cell has been described above as having a channel that comprises a quantum well, it is also foreseen that the channel could instead comprise a semiconductor layer formed of a semiconductor different to that of the semiconductor substrate, provided the conduction band of the channel layer is above the valence band of the semiconductor substrate, and by applying a voltage, at least a portion of the valence band of the semiconductor substrate is raised above the conduction band of the channel.

[0114] The similarities between the memory cell 10 according to the present invention and Flash memory cells readily allows the memory cell 10 disclosed herein to be implemented in Flash architectures, such as NAND type architectures for example, in which a plurality of memory cells are connected in series in large strings.

[0115] The inventor(s) has also discovered that the memory cells disclosed herein may be implemented in an architecture for active memory, ie RAM, which allows fast access to an individual memory cell within an array of memory cells, at the request of a user.

[0116] Such an architecture is possible by implementing the memory cells described above in an architecture as illustrated in FIG. 4. FIG. 4 illustrates a section of a memory device 50 having a plurality of memory cells 10 arranged in an array. The array comprises rows of memory cells 10 electrically connected by wordlines 52A, 52B, 52C, 52D and columns of memory cells 10 electrically connected by bitlines 54-1, 54-2, 54-3, 54-4.

[0117] It is noteworthy in FIG. 4 that the drain terminals of the memory cells 10 are connected in pairs and also connected, in common, to the base gate terminals of all of the cells in the array 50.

[0118] Due to the nature of the resonant tunnelling barrier 28 of the memory cells 10, the current peaks for the write and erase processes are particularly sharp. That is, the voltage required to write or erase to/from the memory cells 10 can be quantified quite specifically. This allows the required voltage to be applied to the memory device 10 via two half-voltages.

[0119] In the example of FIG. 4, a first half-voltage is applied to the target memory cell 56 via wordline 52C, and a second half-voltage is applied to the target memory cell 56 via bitline 54-1. This allows the target memory cell 56 to receive the full voltage required to write/erase to/from the floating gate 26 of the memory cell 56, whilst ensuring that none of the other memory cells 10 along wordline 52C or bitline 54-1 receive enough of a voltage to unintentionally affect storage within their respective floating gates. For example, if it is known that a voltage of 0.8-1V is required to write to the floating gate of a target memory cell, a voltage of 0.5V can be applied to the relevant wordline and 0.5V can be applied to the relevant bitline, such that 1V is supplied to the target memory cell, but only 0.5V is supplied to all of the remaining memory cells, and they remain unaffected. In a similar way, a read operation may be implemented by applying a read threshold voltage to the wordline and testing the conductivity of the cell on the bitline.

[0120] This ability to target individual memory cells within a memory device lends itself to RAM applications, due to its speed of selectively addressing individual cells. However, unlike most RAM technologies, the memory device described above is non-volatile. This method of memory access is also advantageous in that it reduces the number of electrical contacts required, since it only requires electrical contact to each bitline and wordline, because the drain terminals of all the cells in the array are connected to each other and to the common base gate terminal. This allows the memory devices to be much more compact relative to other devices with a similar storage capacity.