METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY PROGRAM ADJUSTMENT FOR MEMORY CELLS EXHIBITING RANDOM TELEGRAPH NOISE

Abstract

A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

Claims

1. A memory device, comprising: a plurality of non-volatile memory cells each comprising a first gate; and a controller configured to program one non-volatile memory cell of the plurality of non-volatile memory cells by: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current.

2. The device of claim 1, wherein each of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between; a floating gate disposed vertically over and insulated from a first portion of the channel region; and a select gate disposed vertically over and insulated from a second portion of the channel region; wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically over and insulated from the floating gate.

3. The device of claim 2, wherein each of the plurality of non-volatile memory cells further comprises: an erase gate disposed over and insulated from the source region.

4. The device of claim 1, wherein the controller is configured to perform the programming of the one non-volatile memory cell to the initial program state by: applying at least one first pulse of programming voltages to the one non-volatile memory cell; reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell that is equal to the target threshold voltage to generate a second read current; and applying at least one second pulse of programming voltages to the one non-volatile memory cell in response to determining that the second read current is greater than the target read current.

5. The device of claim 4, wherein a voltage applied to the first gate as part of the second pulse of programming voltages is greater than a voltage applied to the first gate as part of the first pulse of programming voltages.

6. The device of claim 1, wherein the controller is further configured to: read the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, and subject the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current.

7. The device of claim 1, wherein the controller is further configured to apply a negative voltage to the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation.

8. The device of claim 1, wherein the controller is further configured to apply a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation.

9. The device of claim 6, wherein the controller is further configured to: apply a negative voltage to the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

10. The device of claim 6, wherein the controller is further configured to: apply a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and apply a negative voltage to the first gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

11. A method of programming one non-volatile memory cell of a plurality of non-volatile memory cells, wherein each of the plurality of non-volatile memory cells includes a first gate, the method comprising: programming the one non-volatile memory cell to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the one non-volatile memory cell, wherein the target threshold voltage corresponds to a target read current, reading the one non-volatile memory cell in a first read operation using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a first read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the first read current is greater than the target read current.

12. The method of claim 11, wherein each of the plurality of non-volatile memory cells further comprises: spaced apart source and drain regions formed in a semiconductor substrate, with a channel region of the substrate extending there between; a floating gate disposed vertically over and insulated from a first portion of the channel region; and a select gate disposed vertically over and insulated from a second portion of the channel region; wherein for each of the plurality of non-volatile memory cells, the first gate is disposed vertically over and insulated from the floating gate.

13. The method of claim 12, wherein each of the plurality of non-volatile memory cells further comprises: an erase gate disposed over and insulated from the source region.

14. The method of claim 11, wherein the programming of the one non-volatile memory cell to the initial program state comprises: applying at least one first pulse of programming voltages to the one non-volatile memory cell; reading the one non-volatile memory cell using a read voltage applied to the first gate of the one non-volatile memory cell that is equal to the target threshold voltage to generate a second read current; and applying at least one second pulse of programming voltages to the one non-volatile memory cell in response to determining that the second read current is greater than the target read current.

15. The method of claim 14, wherein a voltage applied to the first gate as part of the second pulse of programming voltages is greater than a voltage applied to the first gate as part of the first pulse of programming voltages.

16. The method of claim 11, further comprising: reading the one non-volatile memory cell in a second read operation, in response to determining that the first read current is not greater than the target read current in the first read operation, using a read voltage applied to the first gate of the one non-volatile memory cell that is less than the target threshold voltage to generate a second read current, and subjecting the one non-volatile memory cell to additional programming in response to determining that the second read current is greater than the target read current.

17. The method of claim 11, further comprising: applying a negative voltage to the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation.

18. The method of claim 11, further comprising: applying a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation.

19. The method of claim 16, further comprising: applying a negative voltage to the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and applying a negative voltage to the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

20. The method of claim 16, further comprising: applying a negative voltage to the first gate of the one non-volatile memory cell after the programming of the one non-volatile memory cell to the initial program state and before the first read operation; and applying a negative voltage to the first gate of the one non-volatile memory cell after the determining that the first read current is not greater than the target read current in the first read operation and before the second read operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG. 1 is a side cross sectional view of a memory cell of the prior art.

[0013] FIG. 2 is a diagram illustrating the components of a memory device.

[0014] FIG. 3 is a flow diagram showing steps for programming memory cells.

[0015] FIG. 4 is a flow diagram showing steps of a first alternate embodiment for programming memory cells.

[0016] FIG. 5 is a flow diagram showing steps of a second alternate embodiment for programming memory cells.

DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention is a technique for compensating for RTN when programming memory cells of the type of FIG. 1 to improve read operation accuracy. The program compensation technique involves detecting memory cells in the memory array that exhibit RTN above a predetermined tolerance level, and compensating programming of those memory cells accordingly.

[0018] The program compensation technique is implemented as part of the controller configuration for the memory array, which can be better understood from the architecture of an exemplary memory device as illustrated in FIG. 2. The memory device includes an array 50 of the non-volatile memory cells 10, which can be segregated into two separate planes (Plane A 52a and Plane B 52b). The memory cells 10 can be of the type shown in FIG. 1, formed on a single chip, arranged in a plurality of rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g. XDEC 54), a source line driver (e.g. SLDRV 56), a column decoder (e.g. YMUX 58), a high voltage row decoder (e.g. HVDEC 60) and a bit line controller (e.g. BLINHCTL 62), which are used to decode addresses and supply the various voltages to the various memory cell gates and regions during read, program, and erase operations for selected memory cells. Column decoder 58 includes a sense amplifier containing circuitry for measuring the currents on the bit lines during a read operation. Controller 66 (containing control circuitry) controls the various device elements to implement each operation (program, erase, read) on target memory cells. Charge pump CHRGPMP 64 provides the various voltages used to read, program and erase the memory cells under the control of the controller 66. Controller 66 is configured to operate the memory device to program, erase and read the memory cells 10. As part of these operations, the controller 66 can be provided with access to the incoming data which is data to be programmed to the memory cells, along with program, erase and read commands provided on the same or different lines. Data read from the memory array is provided as outgoing data.

[0019] The program compensation technique involves the controller 66 implementing memory cell programming, and specifically providing additional programming for memory cells that exhibit an intolerable level of read current instability. This technique involves initially programming memory cell to a particular programming state and taking one or multiple measurements of a memory cell threshold voltage parameter (i.e., a minimum voltage applied to the memory cell to achieve a certain level of source/drain current, referred to as a target current I.sub.target). The preferable threshold voltage parameter is Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate 22. Specifically, the control gate threshold voltage Vtcg is the voltage on the control gate that results in the channel region being a conducting path, and therefore results in a read current through the channel of a predetermined amount (I.sub.target) to consider the memory cell turned on (e.g., 1 μA) when the read potentials of a read operation are applied to the select gate 24 and drain region 16. The control gate threshold voltage Vtcg will vary as a function of programming state of the memory cell, but it is desired that once the memory cell is programmed to a particular programming state, any variation of Vtcg over time be below a predetermined amount.

[0020] An embodiment of the programming technique is illustrated in FIG. 3, which is implemented to program a memory cell to a specific programming state so that it has a target threshold voltage Vtcg.sub.target. The technique begins in Step 1 with programming performed on a memory cell (e.g., a memory cell 10 having the configuration shown in FIG. 1). As described above, this programming operation preferably involves applying programming voltages to the memory cell 10 for a limited time (i.e., in one or more pulses), which results in injecting electrons onto the floating gate 20. In Step 2, a read operation is performed which involves applying read operation voltages to the memory cell 10 and measuring the current flowing through the channel region 18 of the memory cell 10. In this read operation, the voltage Vcg applied to the control gate 22 is the target threshold voltage Vtcg.sub.target. In Step 3, it is determined from the read operation of Step 2 whether or not the threshold voltage Vtcg of the memory cell has reached or exceeded the target threshold voltage Vtcg.sub.target (i.e., whether the channel current I.sub.read is less than or equal to the target current I.sub.target, where I.sub.read equal to the target current I.sub.target is indicative of the threshold voltage Vtcg of the memory cell reaching the target threshold voltage Vtcg.sub.target). If the determination is no (that the threshold voltage Vtcg is not greater than or equal to, i.e. less, than the target threshold voltage Vtcg.sub.target), then in Step 4 the voltage on the control gate Vcg used for programming is optionally increased, and then Step 1 is repeated. Steps 1-4 are repeated in order until it is determined in Step 3 that the threshold voltage Vtcg of the memory cell has reached or exceeded the target threshold voltage Vtcg.sub.target (i.e., that the channel current L.sub.ead is less than or equal to the target current I.sub.target). At that point, the memory cell is considered initially programmed to its desired programming state (i.e. to its target threshold voltage Vtcg.sub.target). It is at this point where conventional programming usually ended.

[0021] However, for the purposes of the present invention, the programming state achieved by Steps 1-4 is only an initial programming state that may call for additional programming. Specifically, if the programmed memory cell exhibits RTN, then electron(s) captured in interface trap(s) contribute to the measured threshold voltage Vtcg of the memory cell as part of programming. If/when the electron(s) are emitted from the interface trap(s) after programming has ended, then the threshold voltage Vtcg could drop by more than ΔVtcg.sub.max below the target threshold voltage Vtcg.sub.target, where ΔVtcg.sub.max is the maximum tolerable read error in terms of Vtcg variation. A threshold voltage drop by more than ΔVtcg.sub.max is considered to be an intolerable error during read operation. Therefore, according the present invention, once there is a read operation that confirms the target threshold voltage Vtcg.sub.target has initially been reached (in Step 3), then, in Step 5, the memory cell is read again, but this time using a control gate voltage Vcg that is less than the target threshold voltage Vtcg.sub.target used in Step 2. Specifically, the control gate voltage Vcg used for this read operation is Vtcg.sub.target−ΔV.sub.tcg, where ΔV.sub.tcg is a relatively small amount and can be defined by the maximum tolerable read error. As a non-limiting example, ΔV.sub.tcg can be equal to ΔVtcg.sub.max which, in turn, depends on specific product and its application, and can be, as an example, 20 mV. In Step 6, it is determined from the read operation of Step 5 whether or not the read current I.sub.read is greater than the target read current I.sub.target. If the memory cell does not exhibit intolerable RTN, then the small decrease in control gate voltage Vcg during the read operation should lower the read current I.sub.read further below I.sub.target, and the determination of Step 6 should be no. In that case, the memory cell can be considered properly programmed. However, if the memory cell does exhibit intolerable RTN, and if before or during this read operation there is interface trap electron emission, then the threshold voltage Vtcg of the memory cell will drop, resulting in a rise in read current I.sub.read. If that rise in current exceeds I.sub.target, then the memory cell is subjected to another round of programming starting at Step 4, and re-read again to confirm it is sufficiently programmed.

[0022] The advantage of the above described technique is that if the memory cell exhibits intolerable RTN, then it will end up getting more deeply programmed (i.e. higher Vtcg) than would otherwise be the case. This means that even if electron emission occurs, it is less likely that the memory cell threshold voltage Vtcg will drop below the target threshold voltage Vtcg.sub.target exceeding the tolerance level of ΔVtcg.sub.max. This is because the memory cell is more deeply programmed above Vtcg.sub.target and future read operations will more accurately reflect the desired programming state of the memory cell within the tolerance level of ΔVtcg variations.

[0023] It has been determined by the present inventors that in certain embodiments improved results can be obtained if Steps 5 and 6 are repeated in the case where the initial determination in Step 6 is negative. Doing so increases the likelihood of identifying if a memory cell exhibits intolerable RTN and therefore should be subjected to additional programming. Therefore, if the initial determination in Step 6 is negative from the first read operation of Step 5, then in Steps 7 and 8, the Steps 5 and 6 are optionally repeated, so that the memory cell is read a second time (Step 7) using Vcg=Vtcg.sub.target−ΔVtcg if the first read operation (Step 5) did not result in a read current greater than I.sub.target, and returned to programming if in Step 8 it is determined I.sub.read exceeds I.sub.target. If the memory cell is twice read using Vcg lower than Vtcg.sub.target, and twice I.sub.read stays below I.sub.target, then the memory cell is considered properly programmed to the target voltage Vtcg.sub.target and programming is completed. Further, while FIG. 3 shows a single repeat of Steps 5 and 6, in certain embodiments even further improved results may be achieved if Steps 5 and 6 are repeated as many times as a user decides to take, whereby the memory cell is subjected to further programming if any single read operation using Vcg=Vtcg.sub.target−ΔVtcg results in a read current I.sub.read that exceeds I.sub.target.

[0024] FIG. 4 illustrates a first alternate embodiment, which is the same method as that described above and depicted in FIG. 3, except Step 3A is added after Step 3. Specifically, once the memory cell is initially programmed to reach its target threshold voltage Vtcg.sub.target (positive determination in Step 3), a negative voltage is applied to the memory cell (e.g. to the control gate, erase gate, and/or select gate). This negative voltage applied to the memory cell induces electric field stress on the gate oxide of the memory cell to stimulate the detrapping (emission) of electrons from the interface and near-interface oxide traps. Preferably, the negative voltage is applied to the control gate, but it can additionally or alternatively be applied to any gate or terminal that is capacitively coupled to the floating gate. Therefore, for a memory cell that has an oxide trap which produces RTN, the negative voltage will stimulate detrapping of electron, setting the threshold voltage Vtcg to a lower Vt state, and increasing the chances that the determination of Step 6 will be positive (and therefore the memory cell will be subjected to additional programming). Since RTN has an erratic behavior, a defective memory cell may stay in one Vtcg state during all read operations, whereby it will not be properly identified for additional programming. Therefore, application of a negative voltage (e.g., −1 V to −7 V) before the read operation of Step 5 will stimulate a memory cell with RTN to exhibit a lower Vt state and, thereby, be identified in Step 6 for additional programming, enhancing programming efficiency and accuracy. There is some characteristic time during which memory cells maintain their Vt state acquired under the applied voltage stress after its removal. Therefore, the delay between the negative voltage application of Step 3A and the read operation of Step 5 should preferably not be longer than typical electron capture and emission time (100 ms at room temperature, as an example), otherwise, application of the negative voltage prior to read operation may be less efficient.

[0025] FIG. 5 illustrates a second alternate embodiment, which is the same method as that described above and depicted in FIG. 4 for the first alternate embodiment, except the negative voltage is not only applied immediately before the initial read operation of Step 5, but it is also applied again before each repeated read operation of Step 5 (see Step 7, which repeats both Step 3A and Step 5, instead of just repeating just Step 5 as indicated in FIG. 4).

[0026] It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein but encompasses any and all variations falling within the scope of any claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely relate to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed unless specified. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa. The terms “forming” and “formed” as used herein shall include material deposition, material growth, or any other technique in providing the material as disclosed or claimed. The example of threshold voltage Vt used in the above described techniques is Vtcg, which is the threshold voltage of the memory cell as viewed from the control gate 22. However, the above described techniques could be implemented with respect to threshold voltage Vt as viewed from any one or more gates in the memory cell that is not floating. Finally, the present invention could be implemented in an array of memory cells with fewer gates than those in FIG. 1 (e.g., no erase gate and/or control gate combined with select gate).