METHOD FOR FABRICATING A METAL-OXIDE-SEMICONDUCTOR TRANSISTOR

Abstract

A semiconductor substrate having a gate dielectric layer and a conductive layer is provided. The conductive layer is patterned into a main gate portion. A drain region and a source region are formed on two sides of the main gate portion, respectively. By thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between a channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region are formed. A first extension gate portion and a second extension gate portion are formed on two opposite sidewalls of the main gate portion, respectively. The main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.

Claims

1. A method for fabricating a metal-oxide-semiconductor (MOS) transistor, comprising: providing a semiconductor substrate having thereon a gate dielectric layer and a first conductive layer; patterning the conductive layer into a main gate portion; performing an ion implantation process to form a drain region and a source region in the semiconductor substrate on two sides of the main gate portion, respectively, wherein a channel region is between the drain region and the source region; thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, thereby forming a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between the channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region, wherein the first portion and the third portion are thinner than the second portion; and forming a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.

2. The method for fabricating a MOS transistor according to claim 1 further comprising: forming a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively.

3. The method for fabricating a MOS transistor according to claim 2, wherein the first dielectric spacer and the second dielectric spacer are situated directly on the first portion and the third portion of the gate dielectric layer, respectively.

4. The method for fabricating a MOS transistor according to claim 2 further comprising: forming a first salicide layer on the drain region and a second salicide layer on the source region.

5. The method for fabricating a MOS transistor according to claim 1, wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.

6. The method for fabricating a MOS transistor according to claim 5, wherein the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer.

7. The method for fabricating a MOS transistor according to claim 1, wherein a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

8. The method for fabricating a MOS transistor according to claim 7, wherein a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

9. The method for fabricating a MOS transistor according to claim 1, wherein the MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

10. A method for fabricating a metal-oxide-semiconductor (MOS) transistor, comprising: providing a semiconductor substrate; forming a drain region, a source region in the semiconductor substrate, and a channel region between the drain region and the source region; forming a gate electrode on the channel region, wherein the gate electrode comprises a main gate portion directly above the channel region, and an extension gate portion on a sidewall of the main gate portion; forming a gate dielectric layer having different thicknesses between the gate electrode and the semiconductor substrate, wherein the extension gate portion of the gate electrode is situated directly on a thinner portion of the gate dielectric layer and the main gate portion of the gate electrode is situated directly on a thicker portion of the gate dielectric layer; and forming a dielectric spacer covering the extension gate portion of the gate electrode, wherein the dielectric spacer is situated directly on the thinner portion of the gate dielectric layer.

11. The method according to claim 10, wherein a first portion of the gate dielectric layer that is situated directly between the drain region and the gate electrode is thinner than a second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode.

12. The method according to claim 11, wherein a third portion of the gate dielectric layer that is situated directly between the source region and the gate electrode is thinner than the second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode.

13. The method according to claim 12, wherein the gate electrode comprises a main gate portion disposed directly above the channel region, and a first extension gate portion and a second extension gate portion disposed on two opposite sidewalls of the main gate portion, respectively.

14. The method according to claim 13, wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.

15. The method according to claim 14, wherein the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer.

16. The method according to claim 13, wherein the main gate portion, the first extension gate portion and the second extension gate portion of the gate electrode are composed of doped polysilicon, silicide, or metal.

17. The method according to claim 13, wherein the first extension gate portion of the gate electrode is covered with a first dielectric spacer and the second extension gate portion of the gate electrode is covered with a second dielectric spacer.

18. The method according to claim 13, wherein a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

19. The method according to claim 18, wherein a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings:

[0019] FIG. 1 is a cross section of a semiconductor memory cell in accordance with one embodiment of the invention;

[0020] FIG. 2 is a cross section of a semiconductor memory cell in accordance with another embodiment of the invention, wherein a triple well is employed;

[0021] FIG. 3 is a schematic diagram showing an exemplary semiconductor memory array composed of the semiconductor memory cell as depicted in FIG. 1;

[0022] FIG. 4 shows the selected memory cell for the program “1” operation in the semiconductor memory array;

[0023] FIG. 5 is a cross section of the selected data storage transistor during the program “1” operation;

[0024] FIG. 6 shows the selected memory cell for the program “0” operation in the semiconductor memory array;

[0025] FIG. 7 is a cross section of the selected data storage transistor during the program “0” operation;

[0026] FIG. 8 is a cross section of the data storage transistor with “1” state during read operation;

[0027] FIG. 9 is a cross section of the data storage transistor with “0” state during read operation; and

[0028] FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary method for fabricating a MOS transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention.

DETAILED DESCRIPTION

[0029] Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

[0030] Embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the embodiments.

[0031] It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types. For example, an NMOS transistor in one embodiment may be replaced with a PMOS transistor in another embodiment without departing from the spirit and scope of the invention.

[0032] The present invention pertains to a MOS transistor having lower gate-to-source/drain breakdown voltage and OTP memory devices using such MOS transistor. The OTP memory devices may comprise a plurality of three-transistor (3T) bit cell structures in the OTP memory array. The OTP memory array utilizes the channel current, instead of ruptured or unruptured dielectric leakage current, for read operations. This invention has a great advantage over the prior art because the state “1” bit current is the transistor “on” current that is consistently high without too much variation other than those caused by manufacture process fluctuation, while the state “0” bit current is the very small transistor “off” current.

[0033] One aspect of the invention provides a semiconductor device including at least an OTP unit cell. A programming path for programming the OTP unit cell is different from a reading path for reading the OTP unit cell. According to some embodiments, the OTP unit cell comprises a programmable MOS transistor that is electrically programmed to “1” state or “0” state. According to some embodiments, the programmable MOS transistor is programmed to the “1” state by rupturing a gate dielectric layer between a gate and a drain of the MOS transistor. According to some embodiments, the programmable MOS transistor is programmed to “0” state by rupturing the gate dielectric layer between the gate and a source of the MOS transistor. According to some embodiments, the gate of the programmable MOS transistor is switched between ground and floating by a switching MOS transistor.

[0034] FIG. 1 is a cross section of a semiconductor memory cell (or OTP unit cell) in accordance with one embodiment of the invention. According to one embodiment of the invention, the illustrated semiconductor memory cell may be a 3T bit cell structure that is included in an OTP memory array. As shown in FIG. 1, the semiconductor memory cell (or OTP unit cell) 1 comprises a read select transistor T.sub.RS that is in series connection with a data storage transistor T.sub.DS for storing a digit “1” or a digital “0” data. The read select transistor T.sub.RS and the data storage transistor T.sub.DS may be constructed on the first active area 101 that is isolated by a first trench isolation structure TI.sub.1. The first active area 101 may be defined on a semiconductor substrate 100 having a first conductivity type, for example, P type. According to one embodiment, for example, the semiconductor substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto.

[0035] The read select transistor T.sub.RS may be used to “select” a memory cell for reading. According to one embodiment of the invention, the read select transistor T.sub.RS comprises a first gate G.sub.1, a first gate dielectric layer OX.sub.1 between the first gate G.sub.1 and the semiconductor substrate 100, a first drain region D.sub.1 in the semiconductor substrate 100 on one side of the first gate G.sub.1, and a first source region S.sub.1 in the semiconductor substrate 100 on the other side of the first gate G.sub.1. According to one embodiment of the invention, the read select transistor T.sub.RS may be an NMOS transistor, and the first drain region D.sub.1 and the first source region S.sub.1 may be N.sup.+ doping regions. The first gate G.sub.1 may be a single polysilicon (or single poly) layer or a metal gate.

[0036] According to one embodiment of the invention, the data storage transistor T.sub.DS comprises a second gate G.sub.2, a second gate dielectric layer OX.sub.2 between the second gate G.sub.2 and the semiconductor substrate 100, a second drain region D.sub.2 in the semiconductor substrate 100 on one side of the second gate G.sub.2, a second source region S.sub.2 in the semiconductor substrate 100 on the other side of the second gate G.sub.2, and a channel region CH between the second drain region D.sub.2 and the second source region S.sub.2. According to one embodiment of the invention, the data storage transistor T.sub.DS may be an NMOS transistor, and the second drain region D.sub.2 and the second source region S.sub.2 may be N.sup.+ doping regions. Likewise, the second gate G.sub.2 may be a single polysilicon layer or a metal gate. Therefore, the read select transistor T.sub.RS and the data storage transistor T.sub.DS constitute two serially connected NMOS transistors on the first active area 101. The N.sup.+ doping region 132 between the first gate G.sub.1 and the second gate G.sub.2 in the semiconductor substrate 100 is commonly shared by the read select transistor T.sub.RS and the data storage transistor T.sub.DS.

[0037] According to one embodiment of the invention, the portions 204 and 206 of the second gate dielectric layer OX.sub.2 that are situated directly between and the second gate G.sub.2 and, respectively the second drain region D.sub.2 and the second source region S.sub.2 are thinner than the portion 202 of the second gate dielectric layer OX.sub.2 that is situated directly between the channel region CH and the second gate G.sub.2. Therefore, the second gate dielectric layer OX.sub.2 has different thicknesses, thereby achieving a lower gate-to-source/drain breakdown voltage of the data storage transistor T.sub.DS.

[0038] Please refer to FIG. 16 for the detailed MOS transistor structure. FIG. 16 is a cross section of an exemplary MOS transistor suited for the data storage transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels. As shown in FIG. 16, the MOS transistor T comprises a semiconductor substrate 100, a drain region 104 and a source region 106 in the semiconductor substrate 100, a channel region CH between the drain region 104 and the source region 106, a gate electrode 210 disposed on the channel region CH, a gate dielectric layer 200 between the gate electrode 210 and the semiconductor substrate 100. The gate dielectric layer 200 has different thicknesses. According to one embodiment of the invention, the portions 204 and 206 of the gate dielectric layer 200 that are situated directly between the gate electrode 210 and, respectively, the drain region 104 and the source region 106 are thinner than the portion 202 of the gate dielectric layer 200 that is situated directly between the channel region CH and the gate electrode 210.

[0039] According to one embodiment of the invention, the gate electrode 210 comprises a main gate portion 212 disposed directly above the channel region CH and two extension gate portions 214 and 216 disposed on two opposite sidewalls of the main gate portion 212. The extension gate portion 214 of the gate electrode 210 is situated directly on the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is situated directly on the portion 206 of the gate dielectric layer 200. The extension gate portion 214 of the gate electrode 210 is in direct contact with the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is in direct contact with the portion 206 of the gate dielectric layer 200. According to one embodiment of the invention, the main gate portion 212, the extension gate portion 214, and the extension gate portion 216 of the gate electrode 210 may be composed of doped polysilicon, silicide, or metal, but is not limited thereto.

[0040] The outer surface of the extension gate portion 214 of the gate electrode 210 is covered with a dielectric spacer 224 and the outer surface of the extension gate portion 216 of the gate electrode 210 is covered with a dielectric spacer 226. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204a of the portion 204 may be aligned with an outer surface of the dielectric spacer 224 and an end surface 206a of the portion 206 may be aligned with an outer surface of the dielectric spacer 226. According to one embodiment of the invention, the dielectric spacer 224 may be situated on the portion 204 of the gate dielectric layer 200 and the dielectric spacer 226 may be situated on the portion 206 of the gate dielectric layer 200.

[0041] According to one embodiment of the invention, the MOS transistor T further comprises a self-aligned silicide (or salicide) layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204a of the portion 204, and the salicide layer 236 is contiguous with the end surface 206a of the portion 206.

[0042] According to one embodiment of the invention, the vertical PN junctions 104a and 106a, which are proximate to the top surface of the semiconductor substrate 100 and are between the channel region CH and, respectively, the drain region 104 and the source region 106 are situated directly underneath the main gate portion 212 of the gate electrode 210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

[0043] Adverting to FIG. 1, the semiconductor memory cell 1 further comprises a program select transistor T.sub.PS that is used to “select” a memory cell for programming. The program select transistor T.sub.PS is constructed on the second active area 102 that is isolated by a second trench isolation structure TI.sub.2. The second active area 102 may be disposed in close proximately to the first active area 101. According to one embodiment of the invention, the program select transistor T.sub.PS comprises a third gate G.sub.3, a third gate dielectric layer OX.sub.3 between the third gate G.sub.3 and the semiconductor substrate 100, a third drain region D.sub.3 in the semiconductor substrate 100 on one side of the third gate G.sub.3, and a third source region S.sub.3 in the semiconductor substrate 100 on the other side of the third gate G.sub.3. The third drain region D.sub.3 is electrically coupled to the second gate G.sub.2.

[0044] According to one embodiment of the invention, the program select transistor T.sub.PS may be an NMOS transistor, and the third drain region D.sub.3 and the third source region S.sub.3 may be N.sup.+ doping regions. Likewise, the third gate G.sub.3 may be a single polysilicon layer or a metal gate.

[0045] In another embodiment, as shown in FIG. 2, the semiconductor memory cell 1a comprising the read select transistor T.sub.RS, the data storage transistor T.sub.DS, and the program select transistor T.sub.PS may be constructed on a triple well structure comprising a deep N well 110 in the P type semiconductor substrate (P Substrate) 100 and a P well 120 isolated from the P type semiconductor substrate 100 by the deep N well 110. During program or read operations, the P well may be biased to a predetermined P well voltage through a P well pickup region (not shown in this figure). It is understood that the illustrated transistors in FIG. 1 and FIG. 2 may further comprise other elements such as spacers on sidewalls of the gates or lightly doped drain (LDD) regions merged with the heavily doped source/drain regions, which are not explicitly shown in the figures for the sake of simplicity.

[0046] According to one embodiment of the invention, during operation, the first drain region D.sub.1 is electrically coupled to a bit line voltage V.sub.BL, the first source region S.sub.1 and the second drain region D.sub.2 (i.e., the N.sup.+ doping region 132) are electrically floating, the second source region S.sub.2 is electrically coupled to a source line voltage V.sub.SL, the third source region S.sub.3 is electrically coupled to ground (GND), the first gate G.sub.1 is electrically coupled to a read select voltage V.sub.Rsel, and the third gate G.sub.3 is electrically coupled to a program select voltage V.sub.Psel.

[0047] FIG. 3 is a diagram showing an exemplary semiconductor memory array composed of the semiconductor memory cell as depicted in FIG. 1. It is understood that although only a 2×3 cell array are shown in FIG. 3, the semiconductor memory array may be an arbitrary N by M array comprising memory cells arranged in N rows and M columns, where N and M are arbitrary numbers. For example, the memory cell MC.sub.0 at the crosspoint of the row R.sub.0 and the column C.sub.0 comprises the read select transistor T.sub.RS, the data storage transistor T.sub.Ds, and the program select transistor T.sub.PS as described in FIG. 1. The first drain region D.sub.1 of the read select transistor T.sub.RS is electrically connected to a bit line BL.sub.0, the second source region S.sub.2 of the data storage transistor T.sub.DS is electrically connected to a source line SL.sub.0, the first gate G.sub.1 of the read select transistor T.sub.RS is electrically connected to a read select line R.sub.sel10 and the third gate G.sub.3 of the program select transistor T.sub.PS is electrically connected to a program select line P.sub.sel10.

[0048] Please refer to Table 1 below, FIG. 4, FIG. 5, and briefly to FIG. 1 and FIG. 2. FIG. 4 shows the selected memory cell (or bit unit) of the semiconductor memory array. FIG. 5 is a cross section of the selected data storage transistor T.sub.DS during the program “1” operation. Table 1 shows exemplary bias conditions for programming digital “1” to the selected semiconductor memory cell in FIG. 4.

TABLE-US-00001 TABLE 1 Program “1” Condition Terminal Bias Voltage Selected P.sub.Sel, V.sub.Psel  1-3 V Unselected P.sub.Sel 0 V Selected R.sub.Sel, V.sub.Rsel 3-10 V Selected BL, V.sub.BL 3-10 V or Ramp up from 0 V till breakdown Unselected BL 0 V or Floating V.sub.SL 0 V or Floating V.sub.PW 0 V or Floating V.sub.PSub/V.sub.DNW 0 V or Floating

[0049] According to one embodiment of the invention, to program the selected bit unit to “1” state, the following bias conditions may be implemented:

[0050] (i) a program select voltage V.sub.Psel of about 1-3V is applied to the selected program select line P.sub.sel (selected P.sub.sel) to turn on the program select transistor T.sub.PS;

[0051] (ii) a high enough read select voltage V.sub.Rsel ranging between, for example, 3-10V may be applied to the selected read select line R.sub.sel (selected R.sub.sel);

[0052] (iii) all the unselected program select lines P.sub.sel (unselected P.sub.sel) and unselected read select lines R.sub.sel (unselected R.sub.sel) are connected to ground GND (or 0V);

[0053] (iv) the semiconductor substrate 100 (e.g., P Substrate) is usually connected to ground (V.sub.PSub=0V), and for the triple well structures as set forth in FIG. 2, the deep N well 110 is connected to ground (V.sub.DNW=0V) while the P well 120 may be floating or connected to ground (V.sub.PW=0V or floating);

[0054] (v) all the source lines SL and unselected bit lines BL are floating or connected to ground (0V); and

[0055] (vi) the selected bit line voltage V.sub.BL is ramped up, preferred to be through a current limiter to prevent overloading the bit line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX.sub.2, indicating dielectric breakdown B, in FIG. 5, directly above the second drain region D.sub.2 of the selected data storage transistor T.sub.DS.

[0056] Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set bit line voltage V.sub.BL that is higher than gate dielectric breakdown voltage (i.e., portion 204 OX.sub.2 breakdown voltage), to the selected bit line, which is also preferred to be done through a current limiter to prevent overloading the bit line voltage supply circuit.

[0057] It is one technical feature of the invention that to write digital “1”, only the thinner portion 204 of the second gate dielectric layer OX.sub.2 that is adjacent to the second drain region D.sub.2 (i.e. drain side dielectric) is ruptured, while the portion 206 of the second gate dielectric layer OX.sub.2 that is adjacent to the second source region S.sub.2 (i.e. source side dielectric) and the portion 202 directly over the channel region CH (i.e. channel dielectric) are remained intact.

[0058] Preferably, the data storage transistor T.sub.Ds may have source junction breakdown voltage and drain junction breakdown voltage, which are higher than the gate dielectric breakdown voltage of the data storage transistor. However, this is not necessary for the embodiments with triple well structures as described in FIG. 2. Further, the gate dielectric breakdown voltage and the junction breakdown voltage of the read select transistor T.sub.RS are both higher than the gate dielectric breakdown voltage of the data storage transistor T.sub.DS. This can be achieved by using thicker gate dielectric or cascoding two transistors for the read select transistor T.sub.RS.

[0059] Please refer to Table 2 below, FIG. 6, FIG. 7, and briefly to FIG. 1 and FIG. 2. FIG. 6 shows the selected memory cell (or bit unit) in the semiconductor memory array. FIG. 7 is a cross section of the selected data storage transistor T.sub.DS during the program “0” operation. Table 2 shows exemplary bias conditions for programming digital “0” to the selected semiconductor memory cell in FIG. 6.

TABLE-US-00002 TABLE 2 Program “0” Condition Terminal Bias Voltage Selected P.sub.Sel, V.sub.Psel 1-3 V All R.sub.Sel 0 V or don't care Unselected P.sub.Sel, 0 V Selected SL, V.sub.SL 3-10 V or Ramp up from 0 V till breakdown Unselected SL 0 V or Floating All BL, V.sub.BL 0 V or Floating P-Well, V.sub.PW 0 V or Floating Others, V.sub.PSub/V.sub.DNW 0 V or Floating

[0060] According to one embodiment of the invention, to program the selected bit unit to “0” state, the following bias conditions may be implemented:

[0061] (i) a program select voltage V.sub.Psel of about 1-3V is applied to the selected program select line P.sub.sel (selected P.sub.sel) to turn on the program select transistor T.sub.PS;

[0062] (ii) all the unselected program select lines P.sub.sel (unselected P.sub.sel) are connected to ground (or 0V);

[0063] (iii) all the read select lines R.sub.sel are connected to 0V or don't care;

[0064] (iv) the semiconductor substrate 100 (e.g., P Substrate) is usually connected to ground (0V), and for the triple well structures as set forth in FIG. 2, the deep N well 110 is connected to ground (V.sub.DNW=0V) while the P well 120 may be floating or connected to ground (V.sub.PW=0V or floating);

[0065] (v) all the bit lines BL and unselected source lines SL are floating or connected to ground; and

[0066] (vi) the selected source line voltage V.sub.SL is ramped up, preferred to be through a current limiter to prevent overloading the source line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX.sub.2, indicating dielectric breakdown B, in FIG. 7, directly on the second source region S.sub.2 of the selected data storage transistor T.sub.DS.

[0067] Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set source line voltage V.sub.SL that is higher than gate dielectric breakdown voltage (i.e., portion 206 of OX.sub.2breakdown voltage), to the selected source line, which is also preferred to be through a current limiter to prevent overloading the source line voltage supply circuit.

[0068] It is another technical feature of the invention that to write digital “0”, only the portion 206 of the second gate dielectric layer OX.sub.2 that is adjacent to the second source region S.sub.2 (i.e. source side dielectric) is ruptured, while the portion 204 of the second gate dielectric layer OX.sub.2 that is adjacent to the second drain region D.sub.2 (i.e. drain side dielectric) and the portion 202 directly over the channel region CH (i.e. channel dielectric) are remained intact.

[0069] Please refer to Table 3 below, FIG. 8 and FIG. 9. FIG. 8 is across section of the data storage transistor T.sub.DS with “1” state during read operation. FIG. 9 is a cross section of the data storage transistor T.sub.DS with “0” state during read operation. Table 3 shows exemplary bias conditions for reading data storage transistor T.sub.DS.

[0070] To read a memory cell, the following exemplary bias conditions may be implemented:

[0071] (i) all the program select lines P.sub.sel are connected to ground (0V) to turn off all program select transistors T.sub.PS so that all the second gates G.sub.2 of the data storage transistors T.sub.DS are isolated from the outside bias. Therefore, voltage of the second gate G.sub.2 of the data storage transistors T.sub.DS is the same as that of second drain region D.sub.2 if the dielectric breakdown B, caused during the programming procedure, is on the drain side, and the same as that of second source region S.sub.2 if the dielectric breakdown B is on the source side;

[0072] (ii) a read select voltage V.sub.Rsel of about 1-3V is applied to the selected read select lines R.sub.sel so that drain of the selected data storage transistors T.sub.DS is connected to the selected bit line BL to which a bit line voltage V.sub.BL of 0.5-2V is applied; and

[0073] (iii) all the other terminals are connected to ground (0V).

TABLE-US-00003 TABLE 3 Read Bias Condition Terminal Bias Voltage All P.sub.Sel 0 V Selected R.sub.Sel   1-3 V Unselected R.sub.Sel, 0 V Selected BL 0.5-2 V Unselected BL 0 V or Floating All SL 0 V P-Well 0 V Others 0 V

[0074] Under the aforesaid read bias conditions, the data storage transistors T.sub.DS has a high channel current CL if the dielectric breakdown B is on the drain side because the gate voltage is high, same as the voltage applied to the second drain region D.sub.2, and the data storage transistors T.sub.DS (“1” state) is turned on, as shown in FIG. 8. On the other hand, for the data storage transistors T.sub.DS in “0” state, there is no channel current (or only an insignificant amount of off-current) because the voltage coupled to the second gate G.sub.2 is low, same as the voltage applied to the second source region S.sub.2, and the data storage transistors T.sub.DS (“0” state) is turned off, as shown in FIG. 9. Therefore, the read current path is not through the ruptured dielectric, but is through the channel region CH of the data storage transistor T.sub.DS.

[0075] According to some embodiments, all the isolated second gates G.sub.2 of the data storage transistors T.sub.DS may be pre-charged by turning on all read select transistors T.sub.R simultaneously and applying 0.5-2V to all bit lines and 0V to all source line for a short period of time (e.g., 3 ms) prior to reading the entire OTP memory array. This can prevent those soft breakdown bits from errors due to slow charging.

[0076] FIG. 10 to FIG. 17 are schematic diagrams showing an exemplary method for fabricating a MOS transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels.

[0077] As shown in FIG. 10, a semiconductor substrate 100 such as a P type silicon substrate is provided. A gate dielectric layer 200 such as silicon dioxide (SiO.sub.2), silicon oxynitride (SiON) or hafnium dioxide (HfO.sub.2), or the combination of two or more is deposited on the semiconductor substrate 100. According to one embodiment, the gate dielectric layer 200 may have a thickness of about 2-20 nm, but is not limited thereto. A first conductive layer 210a such as N-doped polysilicon, silicide or metal is then deposited on the gate dielectric layer 200. For example, the first conductive layer 210a is an N-doped polysilicon layer. According to one embodiment, the first conductive layer 210a may have a thickness of about 80-200 nm, but is not limited thereto. Optionally, a cap nitride layer 230 may be deposited on the first conductive layer 210a. For example, the cap nitride layer 230 may be a silicon nitride layer and may have a thickness of about 5-10 nm.

[0078] It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types.

[0079] Subsequently, as shown in FIG. 11, a photoresist pattern PR is formed on the cap nitride layer 230 to define gate area. An anisotropic etching process 500 is then performed to remove the cap nitride layer 230 and the first conductive layer 210a not covered by the photoresist pattern PR, thereby forming a main gate portion 212. At this point, the gate dielectric layer 200 is substantially not etched.

[0080] As shown in FIG. 12, the remaining photoresist pattern PR is removed. An ion implantation process 600 is then performed to implant N type dopants into the semiconductor substrate 100, thereby forming N.sup.+ drain region 104 and N.sup.+ source region 106. According to one embodiment, the N.sup.+ drain region 104 and N.sup.+ source region 106 may be formed with graded junction, which may be formed by using, for example, doubly diffused method, for higher junction breakdown voltage.

[0081] As shown in FIG. 13, an etching process is performed to remove an upper portion of the gate dielectric layer 200, thereby forming a thinner portions 204 and 206 on the N.sup.+ drain region 104 and N.sup.+ source region 106, respectively. The portions 204 and 206 may be thinned down to thickness of 30-70% of the original thickness. According to one embodiment, the etching process may be a wet etching process, but is not limited thereto. It is understood that in some embodiments the ion implantation process 600 in FIG. 12 may be performed after gate dielectric thinning down.

[0082] As shown in FIG. 14, a second conductive layer 210b such as N-doped polysilicon, silicide or metal is deposited on the semiconductor substrate 100. The second conductive layer 210b conformally covers the main gate portion 212 and the thinner portions 204 and 206. The second conductive layer 210b is in direct contact with the sidewalls of the main gate portion 212. For example, the second conductive layer 210b is an N-doped polysilicon layer. According to one embodiment, the second conductive layer 210b may have a thickness of about 20-100 nm,

[0083] As shown in FIG. 15, an anisotropic etching process 700 is then performed to etch the second conductive layer 210b, thereby forming extension gate portions 214 and 216 on the opposite sidewalls of the main gate portion 212. The extension gate portion 214 is situated directly on the portion 204 of the gate dielectric layer 200 and the extension gate portion 216 of the gate electrode 210 is situated directly on the portion 206 of the gate dielectric layer 200.

[0084] As shown in FIG. 16, the cap nitride layer 230 is removed, optionally. After the removal of the cap nitride layer 230, the top surface of the main gate portion 212 is revealed. Subsequently, a dielectric spacer 224 and a dielectric spacer 226 are formed on the gate dielectric layer 200 and the extension gate portions 214 and 216 of the gate electrode 210, respectively. Removal of cap nitride layer 230 can also be achieved during formation of spacer 224 and spacer 226. The formation of the dielectric spacers 224 and 226 may involve conformal deposition of a spacer material layer and anisotropic etch of the spacer material layer. In some embodiments, the cap nitride layer 230 is not removed prior to the conformal deposition of the spacer material layer, and the cap nitride layer 230 can be removed during anisotropic etch of the spacer material layer.

[0085] The outer surface of the extension gate portion 214 of the gate electrode 210 is covered with the dielectric spacer 224 and the outer surface of the extension gate portion 216 of the gate electrode 210 is covered with the dielectric spacer 226. According to one embodiment of the invention, for example, the dielectric spacers 224 and 226 may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface 204a of the portion 204 is aligned with an outer surface of the dielectric spacer 224 and an end surface 206a of the portion 206 is aligned with an outer surface of the dielectric spacer 226.

[0086] A self-aligned silicidation process is then performed to form a salicide layer 232 on the gate electrode 210, a salicide layer 234 on the drain region 104, and a salicide layer 236 on the source region 106. According to one embodiment of the invention, salicide layers 232, 234 and 236 may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer 234 is contiguous with the end surface 204a of the portion 204, and the salicide layer 236 is contiguous with the end surface 206a of the portion 206. According to one embodiment of the invention, the salicide layer 234 is not in direct contact with the dielectric spacer 224, and salicide layer 236 is not indirect contact with the dielectric spacer 226.

[0087] According to one embodiment of the invention, the vertical PN junctions 104a and 106a proximate to the top surface of the semiconductor substrate 100 are situated directly underneath the main gate portion 212 of the gate electrode 210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

[0088] As shown in FIG. 17, an interlayer dielectric (ILD) layer 240 is then deposited on the semiconductor substrate 100. The ILD layer 240 covers the MOS transistor T. Subsequently, a contact plug 244 and a contact plug 246 may be formed in the ILD layer 240. An interconnect structure 254 and an interconnect structure 256 may be formed on the ILD layer 240. The interconnect structure 254 is electrically connected to the drain region 104 through the contact plug 244. The interconnect structure 256 is electrically connected to the source region 106 through the contact plug 246.

[0089] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.