SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device (A1) includes a semiconductor layer having a first face with a trench (3) formed thereon and a second face opposite to the first face, a gate electrode (41), and a gate insulating layer (5). The semiconductor layer includes a first n-type semiconductor layer (11), a second n-type semiconductor layer (12), a p-type semiconductor layer (13), and an n-type semiconductor region (14). The trench (3) is formed so as to penetrate through the p-type semiconductor layer (13) and to reach the second n-type semiconductor layer (12). The p-type semiconductor layer (13) includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench (3) is. Such structure allows suppressing dielectric breakdown in the gate insulating layer (5).

Claims

1-8. (canceled)

9. A semiconductor device comprising: a layer of semiconductor having a first face and a second face opposite to the first face, the first face being provided with a first trench and a second trench adjacent to the first trench; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a first insulating layer provided in the first trench for insulating the layer of semiconductor and the first gate electrode from each other; and a second insulating layer provided in the second trench for insulating the layer of semiconductor and the second gate electrode from each other; wherein the layer of semiconductor includes a first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, the second semiconductor layer being generally closer to the first face than is the first semiconductor layer, wherein each of the first trench and the second trench extends through the second semiconductor layer and reaches the first semiconductor layer, the second semiconductor layer includes: a close portion that is close to the second face of the layer of semiconductor and disposed between the first trench and the second trench; and a sublayer disposed farther from the second face of the layer of semiconductor than is the close portion, the second semiconductor layer includes a first channel region formed along the first trench and in contact with the first semiconductor layer and a second channel region formed along the second trench and in contact with the first semiconductor layer, the close portion is spaced apart from each of the first trench and the second trench so that an upper interface of the close portion is at a same or substantially same height with a lower interface of each of the first channel region and the second channel region, and the layer of semiconductor further comprises a first semiconductor region and a second semiconductor region of the second conductivity type, the first semiconductor region being formed around a bottom portion of the first trench, the second semiconductor region being formed along a bottom portion of the second trench, the first trench and the second trench are symmetrical with respect to a center line of the close portion.

10. The semiconductor device according to claim 9, wherein the layer of semiconductor comprises a wide band gap semiconductor.

11. The semiconductor device according to claim 10, wherein the layer of semiconductor is made of SiC.

12. The semiconductor device according to claim 11, further comprising a contact region between the first trench and the second trench.

13. The semiconductor device according to claim 12, further comprising a source region formed at a surface of the layer of the semiconductor.

14. The semiconductor device according to claim 13, wherein the source region is formed between the contact region and one of the first trench or the second trench.

15. The semiconductor device according to claim 14, further comprising a first insulating film and a second insulating film formed over the first gate electrode and the second gate electrode, respectively.

16. The semiconductor device according to claim 15, further comprising a source electrode formed over the first insulating film, the second insulating film and the first face of the layer of semiconductor.

17. The semiconductor device according to claim 16, wherein a surface of the source electrode includes an unevenness formed due to a thickness of each of the first insulating film and the second insulating film.

18. The semiconductor device according to claim 17, wherein a distance from the first trench to the contact region is same as a distance from the second trench to the contact region.

19. The semiconductor device according to claim 18, wherein a width of the contact region is smaller than a width of the close portion.

20. The semiconductor device according to claim 19, wherein a thickness of the close portion is greater than a thickness of the contact region.

21. The semiconductor device according to claim 20, wherein each of the first semiconductor region and the second semiconductor region includes a curved outline portion.

22. The semiconductor device according to claim 21, wherein an interface between the bottom of the first trench and the first semiconductor region is formed between an upper part of the close portion and an lower part of the close portion in a cross sectional view.

23. The semiconductor device according to claim 22, wherein an interface between the bottom of the second trench and the second semiconductor region is formed between the upper part of the close portion and the lower part of the close portion in a cross sectional view.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

[0018] FIG. 2 is a fragmentary cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 1;

[0019] FIG. 3 is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 2;

[0020] FIG. 4 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention;

[0021] FIG. 5A is a fragmentary cross-sectional view for explaining a manufacturing process of the semiconductor device shown in FIG. 4;

[0022] FIG. 5B is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 5A;

[0023] FIG. 6 is a fragmentary cross-sectional view of a semiconductor device according to a third embodiment of the present invention;

[0024] FIG. 7 is a fragmentary cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention;

[0025] FIG. 8A is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 7;

[0026] FIG. 8B is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 8A;

[0027] FIG. 9A is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 8B;

[0028] FIG. 9B is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 9A;

[0029] FIG. 10 is a fragmentary cross-sectional view for explaining a manufacturing process following the state shown in FIG. 9B;

[0030] FIG. 11 is a fragmentary cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention; and

[0031] FIG. 12 is a fragmentary cross-sectional view of a conventional semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

[0032] Hereunder, preferred embodiments of the present invention will be described in details, referring to the drawings.

[0033] FIG. 1 illustrates a semiconductor device according to a first embodiment of the present invention. The semiconductor device A1 according to this embodiment includes a first n-type semiconductor layer 11, a second n-type semiconductor layer 12, a p-type semiconductor layer 13, an n-type semiconductor region 14, a high-concentration p-type semiconductor region 13a, a trench 3, a gate electrode 41, a gate insulating layer 5, a source electrode 42, a drain electrode 43 and an interlayer dielectric 6.

[0034] The first n-type semiconductor layer 11 is a substrate constituted of silicon carbide with a high-concentration impurity added thereto. The second n-type semiconductor layer 12 is provided on the first n-type semiconductor layer 11. The second n-type semiconductor layer 12 is constituted of silicon carbide with a low-concentration impurity added thereto.

[0035] The p-type semiconductor layer 13 includes a first p-type semiconductor layer 131 and a second p-type semiconductor layer 132. The first p-type semiconductor layer 131 is provided on the second n-type semiconductor layer 12. Of the boundary between the first p-type semiconductor layer 131 and the second n-type semiconductor layer 12, a portion along a depthwise direction x of the trench 3 will be referred to as a lateral boundary K1, and a portion along a widthwise direction y will be referred to as a bottom boundary K2. In this embodiment, the bottom boundary K2 is spaced from the boundary between the n-type semiconductor region 14 and the source electrode 42, by approximately 1 μm. The impurity concentration of the first p-type semiconductor layer 131 is, for example, 1×10.sup.17 cm.sup.−3 to 1×10.sup.20 cm.sup.−3. The second p-type semiconductor layer 132 is provided on the first p-type semiconductor layer 131 and the second n-type semiconductor layer 12. Of the boundary between the second p-type semiconductor layer 132 and the second n-type semiconductor layer 12, a portion along the widthwise direction y will be referred to as a bottom boundary K3. The impurity concentration of the second p-type semiconductor layer 132 is, for example, 1×10.sup.16 cm.sup.−3 to 1×10.sup.19 cm.sup.−3. The n-type semiconductor region 14 is provided on the p-type semiconductor layer 13. The high-concentration p-type semiconductor region 13a is provided on the first p-type semiconductor layer 131.

[0036] The trench 3 is formed so as to penetrate through the n-type semiconductor region 14 and the second p-type semiconductor layer 132, and to reach the second n-type semiconductor layer 12. The trench 3 and the first p-type semiconductor layer 131 are spaced from each other by approximately 0.3 μm, when viewed in the widthwise direction y.

[0037] Inside the trench 3, the gate electrode 41 and the gate insulating layer 5 are located. The gate electrode 41 is constituted of, for example, polysilicon. Alternatively, a metal such as aluminum may be employed to form the gate electrode 41. The gate insulating layer 5 is constituted of silicon dioxide for example, and serves to insulate the gate electrode 41 from the second n-type semiconductor layer 12, the p-type semiconductor layer 13, and the n-type semiconductor region 14. The gate insulating layer 5 is provided along the inner wall of the trench 3 and over the bottom portion and the lateral portion of the trench 3.

[0038] In the depthwise direction x, the bottom boundary K3, the bottom portion of the gate electrode 41, the bottom portion of the trench 3, and the bottom boundary K2 are located in the mentioned order, downwardly in FIG. 1.

[0039] The source electrode 42 is for example constituted of aluminum, and located in contact with the n-type semiconductor region 14 and the high-concentration p-type semiconductor region 13a. The drain electrode 43 is also constituted of aluminum for example, and located in contact with the first n-type semiconductor layer 11. The drain electrode 43 is provided on the opposite side of the first n-type semiconductor layer 11 to the second n-type semiconductor layer 12. The interlayer dielectric 6 is formed so as to cover the gate electrode 41.

[0040] Now, an example of the manufacturing method of the semiconductor device A1 will be described, referring to FIGS. 2 and 3.

[0041] Referring first to FIG. 2, a semiconductor substrate which is to serve as the first n-type semiconductor layer 11 is prepared. On the upper surface of the substrate, the second n-type semiconductor layer 12 is formed through epitaxial crystal growth. Then a groove T1 is formed on the surface of the second n-type semiconductor layer 12.

[0042] Referring then to FIG. 3, the first p-type semiconductor layer 131 is formed inside the groove T1 through the epitaxial crystal growth. The surface of the substrate is then planarized. On the planarized substrate, the second p-type semiconductor layer 132 is formed through the epitaxial crystal growth.

[0043] Then a mask of a predetermined pattern is placed over the upper surface of the second p-type semiconductor layer 132, and impurity ions (n-type or p-type) are injected. Thus the n-type semiconductor region 14 and the high-concentration p-type semiconductor region 13a are formed.

[0044] The above is followed by the formation of the trench 3, the gate insulating layer 5 and the gate electrode 41 shown in FIG. 1. Then the interlayer dielectric 6, the source electrode 42, and the drain electrode 43 are formed. Through the foregoing process, the semiconductor device A1 can be obtained.

[0045] The advantageous effects of the semiconductor device A1 will now be described hereunder. In this embodiment, the bottom boundary K2 is at a lower level than the bottom portion of the trench 3, according to the orientation of FIG. 1. Such configuration encourages the field concentration on the boundary between the first p-type semiconductor layer 131 and the second n-type semiconductor layer 12. Accordingly, the field concentration on the bottom portion of the trench 3 is mitigated. Mitigating the field concentration reduces the risk of dielectric breakdown in the gate insulating layer 5. As a result, the withstand voltage of the semiconductor device A1 can be improved.

[0046] The structure according to this embodiment allows reducing the impurity concentration of the second p-type semiconductor layer 132. This facilitates lowering the threshold voltage of the semiconductor device A1. On the other hand, increasing the impurity concentration of the first p-type semiconductor layer 131 allows suppressing extension of a depletion layer in the first p-type semiconductor layer 131, thereby preventing a punch through phenomenon.

[0047] FIGS. 4, 5A and 5B illustrate a second embodiment of the present invention. In these drawings, the constituents same as or similar to those of the foregoing embodiment are given the same numeral. The semiconductor device A2 according to this embodiment is different from the semiconductor device A1 according to the first embodiment in including a recessed portion T2.

[0048] In the semiconductor device A2 shown in FIG. 4, the impurity concentration in the first p-type semiconductor layer 131 is higher than that in the second p-type semiconductor layer 132, as in the first embodiment.

[0049] Above the first p-type semiconductor layer 131 according to the orientation of FIG. 4, a recessed portion T2 is provided. In this embodiment, the size of the opening of the recessed portion T2 in the widthwise direction y is slightly smaller than that of the first p-type semiconductor layer 131 in the widthwise direction y. The bottom portion of the recessed portion T2 is located higher than the bottom boundary K2, according to FIG. 4. Also, the bottom portion of the recessed portion T2 is located higher than the bottom boundary K3 in FIG. 4. The high-concentration p-type semiconductor region 13a is located below the recessed portion T2. It is not mandatory that the bottom portion of the recessed portion T2 is located higher than the bottom boundary K3. For example, the bottom portion of the recessed portion T2 may be located lower than the bottom portion of the trench 3. The position of the bottom portion of the recessed portion T2 may be determined irrespective of the position of the bottom boundary K3 and the bottom portion of the trench 3.

[0050] Referring now to FIGS. 5A and 5B, an example of the manufacturing method of the semiconductor device A2 will be described hereunder.

[0051] First, as shown in FIG. 5A, a semiconductor substrate which is to serve as the first n-type semiconductor layer 11 is prepared. On the upper surface of the substrate, the second n-type semiconductor layer 12 is formed through the epitaxial crystal growth. Then the recessed portion T2 is formed on the surface of the second n-type semiconductor layer 12, in a depth of approximately 0.5 μm.

[0052] Referring then to FIG. 5B, the first p-type semiconductor layer 131 is formed. To form the first p-type semiconductor layer 131, a mask (not shown) is placed over the upper surface of the substrate, and the recessed portion T2 is irradiated with impurity ions (p-type) from above in FIG. 5B, with energy of approximately 400 KeV. Then the region on the surface of the second n-type semiconductor layer 12 where the recessed portion T2 is not formed is irradiated with impurity ions (p-type), with generally the same energy. As a result, the second p-type semiconductor layer 132 is formed. Here, the ion concentration in the first p-type semiconductor layer 131 and the second p-type semiconductor layer 132 can be controlled by adjusting the duration of the ion irradiation.

[0053] Alternatively, the entire surface of the second n-type semiconductor layer 12 may be irradiated with impurity ions from above in FIG. 5B, without putting the mask on the upper surface of the substrate. By such impurity ion irradiation, the first p-type semiconductor layer 131 and the second p-type semiconductor layer 132 can be formed in different depths from the surface of the second n-type semiconductor layer 12. This process is especially useful in the case where it is not necessary to control the impurity concentration in the first p-type semiconductor layer 131 and the second p-type semiconductor layer 132.

[0054] The above is followed by the formation of the n-type semiconductor region 14 and the high-concentration p-type semiconductor region 13a shown in FIG. 4. These regions can also be formed by injecting impurity ions (n-type or p-type) to the second n-type semiconductor layer 12. Then the trench 3 is formed in the region where the second p-type semiconductor layer 132 has been formed. Inside the trench 3, the gate insulating layer 5 and the gate electrode 41 are formed. Then the interlayer dielectric 6, the source electrode 42, and the drain electrode 43 are formed. Through the foregoing process, the semiconductor device A2 can be obtained.

[0055] According to this embodiment, providing the recessed portion T2 allows forming a deeper portion of the first p-type semiconductor layer 131 by the ion irradiation with lower energy.

[0056] FIG. 6 illustrates a third embodiment of the present invention. As in the preceding drawings, the constituents in FIG. 6 same as or similar to those of the foregoing embodiments are given the same numeral. The semiconductor device A3 according to this embodiment is different from the semiconductor device A2 according to the second embodiment in that the n-type semiconductor region is also provided under the recessed portion T2. Such configuration increases the contact area between the source electrode 42 and the n-type semiconductor region 14. Accordingly, the contact resistance between the source electrode 42 and the n-type semiconductor region 14 can be reduced, in the semiconductor device A3.

[0057] FIGS. 7 to 10 illustrate a fourth embodiment of the present invention. In these drawings, the constituents same as or similar to those of the foregoing embodiments are given the same numeral. The semiconductor device A4 according to this embodiment is different from the semiconductor device A1 according to the first embodiment in including a p-type semiconductor region 15.

[0058] As is apparent in FIG. 7, the p-type semiconductor region 15 is located in contact with the bottom portion of the trench 3. The impurity concentration in the p-type semiconductor region 15 is, for example, 1×10.sup.16 cm.sup.−3 to 1×10.sup.21 cm.sup.−3. The size of the boundary between the p-type semiconductor region 15 and the bottom portion of the trench 3 in the widthwise direction y is slightly smaller than that of the gate electrode 41 in the widthwise direction y. Also, a lowermost portion of the p-type semiconductor region 15 according to the orientation of FIG. 7 is located lower than the bottom boundary K2 in the depthwise direction x. Conversely, although not shown, the bottom boundary K2 may be located lower than the lowermost portion of the p-type semiconductor region 15.

[0059] Referring now to FIGS. 8 to 10, an example of the manufacturing method of the semiconductor device A4 will be described hereunder.

[0060] The manufacturing method of the semiconductor device A4 is the same as that of the semiconductor device A1 according to the first embodiment, up to the state shown in FIG. 3. Accordingly, the description of the process up to FIG. 3 is not repeated. Referring thus to FIG. 8A, a plasma CVD is performed over the upper surface of the structure shown in FIG. 3, to thereby forma silicon dioxide layer 7. The silicon dioxide layer 7 serves as the mask for forming the trench 3 and the p-type semiconductor region 15, as will be subsequently described. Proceeding to FIG. 8B, a trench 3′ is formed so as to penetrate through all of the silicon dioxide layer 7, the n-type semiconductor region 14, and the p-type semiconductor layer 13. The trench 3′ is to be formed into the trench 3 shown in FIG. 7. Then the inner wall of the trench 3′ is thermally oxidized (not shown).

[0061] Then as shown in FIG. 9A, a polysilicon layer ps is formed all over the inner wall of the trench 3′ and the upper surface of the silicon dioxide layer 7. Then as shown in FIGS. 9B and 10, a polysilicon layer ps1 and a polysilicon layer ps3 are removed, leaving a polysilicon layer ps2 unremoved. Impurity ions (p-type) are then injected to the bottom portion of the trench 3′, as shown in FIG. 10. At this stage, the p-type semiconductor region 15 is formed. Then the entirety of the silicon dioxide layer 7 and the polysilicon layer ps2 are removed. This is followed by the same process as that described in the first embodiment. Thus, the semiconductor device A4 shown in FIG. 7 can be obtained.

[0062] The advantageous effects of the semiconductor device A4 will now be described hereunder.

[0063] The structure of the semiconductor device A4 allows further mitigating the field concentration on the bottom portion of the trench 3. Accordingly, the withstand voltage of the semiconductor device A4 can be further improved. Here, reducing the size of the p-type semiconductor region 15 in the widthwise direction y allows suppressing an increase in on-resistance.

[0064] FIG. 11 illustrates a fifth embodiment of the present invention. In FIG. 11, the constituents same as or similar to those of the foregoing embodiments are given the same numeral. A difference between the semiconductor device A5 according to this embodiment and the semiconductor device A4 according to the fourth embodiment lies in the shape of the trench 3.

[0065] As shown in FIG. 11, the additional p-type semiconductor layer 15 is provided so as to cover the bottom portion of the trench 3. Such configuration allows further increasing the withstand voltage. Also, the bottom portion of the trench 3 is formed in a trapezoidal shape. As a result, the additional p-type semiconductor layer 15 can be formed within an area overlapping with the trench 3 in the widthwise direction y. The foregoing structure prevents the flow of electron in the semiconductor device A5 from being disturbed, thereby suppressing an increase in on-resistance. Consequently, the dielectric breakdown electric field can be further increased, while an increase in on-resistance can be suppressed.

[0066] The semiconductor device and the manufacturing method of the same according to the present invention are not limited to the foregoing embodiments. Specific structure and arrangement of the semiconductor device and the manufacturing method according to the present invention may be varied in different manners.