A display apparatus includes: a substrate; a first semiconductor layer disposed over the substrate; a first insulating layer disposed on the first semiconductor layer; a second insulating layer disposed on the first insulating layer; a first oxide material layer disposed between the substrate and the second insulating layer; and a first conductive layer disposed on the second insulating layer and electrically connected to the first semiconductor layer through a first contact hole defined in the first insulating layer, the second insulating layer, and the first oxide material layer.

An object of the present disclosure is to provide a trench gate type power semiconductor device that does not easily break even when stress is applied. A SiC-MOSFET includes a SiC substrate, a drift layer of a first conductive type, formed on the SiC substrate, a base region of a second conductivity type formed in a surface layer of the drift layer, a source region of the first conductivity type selectively formed in a surface layer of the base region, a trench extending through the base region and the source region and reaching the drift layer, a gate electrode embedded in the trench and having a V-shaped groove on an upper surface thereof, and an oxide film formed on an upper surface including the groove of the gate electrode, in which a bottom of the V-shape groove is deeper than the base region.

A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n.sup.+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n.sup.+ type drain contact region and the p type element isolation region.

A multi-trench super junction IGBT device includes a metallization collector, a P-type substrate, a first N-type epitaxial layer located above the P-type substrate and a second N-type epitaxial layer located above the first N-type epitaxial layer. The second N-type epitaxial layer includes at least a first dummy MOS cell unit and a MOS cell unit, wherein the first dummy MOS cell unit includes a trench formed by reactive ion etching, a thermally grown gate oxide layer provided inside the trench and deposited heavily doped polysilicon located in the gate oxide layer.

An integrated circuit (IC) device includes a chip having a semiconductor substrate and a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

An integrated circuit (IC) device includes a chip having a semiconductor substrate and a thermoelectric module embedded in the semiconductor substrate, where the thermoelectric module includes a first semiconductor structure electrically connected to a second semiconductor structure, where a bottom portion of thermoelectric module extends through a thickness of the semiconductor substrate, and where the first semiconductor structure and the second semiconductor structure include dopants of different conductivity types.

Bi-directional trench power switches. At least one example is a semiconductor device comprising: an upper base region associated with a first side of a substrate of semiconductor material; an upper-CE trench defined on the first side, the upper-CE trench defines a proximal opening at the first side and a distal end within the substrate; an upper collector-emitter region disposed at the distal end of the upper-CE trench; a lower base region associated with a second side of substrate; and a lower collector-emitter region associated with the second side.

A semiconductor device includes a backside contact and a substrate. An epitaxial field stop region may be formed on the substrate with a graded doping profile that decreases with distance away from the substrate, and an epitaxial drift region may be formed adjacent to the epitaxial field stop region. A frontside device may be formed on the epitaxial drift region.

A semiconductor device comprises an active pattern on a substrate, a pair of first source/drain patterns on the active pattern, a pair of second source/drain patterns on top surfaces of the first source/drain patterns, a gate electrode extending across the active pattern and having sidewalls that face the first and second source/drain patterns, a first channel structure extending across the gate electrode and connecting the first source/drain patterns, and a second channel structure extending across the gate electrode and connecting the second source/drain patterns. The gate electrode includes a first lower part between a bottom surface of the first channel structure and a top surface of the active pattern, and a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure. The first lower part has a thickness greater than that of the first upper part.

An improved inverted field-effect-transistor semiconductor device and method of making thereof may comprise a source layer on a bottom and a drain disposed on a top of a semiconductor substrate and a vertical current conducting channel between the source layer and the drain controlled by a trench gate electrode disposed in a gate trench lined with an insulating material. A heavily doped drain region is disposed near the top of the substrate surrounding an upper portion of a shield trench and the gate trench. A doped body contact region is disposed in the substrate and surrounding a lower portion of the shield trench. A shield electrode extends upward from the source layer in the shield trench for electrically shorting the source layer and the body region wherein the shield structure extends upward to a heavily doped drain region and is insulated from the heavily doped drain region to act as a shield electrode.