High-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor and preparation method thereof

Abstract

This disclosure provides a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor and a preparation method thereof. An InGaP material has characteristics of a high carrier mobility of the InP material and a forbidden band width of the GaP material, so that the present disclosure employs the N-type In.sub.1-xGa.sub.xP layer as the collector to improve the frequency and power characteristics of the device, and realize the system integration of terahertz band chips. Further, the present disclosure utilizes the characteristics of the above materials and takes an advantages of “energy band engineering”, uses the In.sub.1-xGa.sub.xP (x=0-1) is used as the material of the collector of the SiGe-HBT, the composition molar ratio X of In and Ga is appropriately selected, such that the materials SiGe of the collector and the sub-collector have the same lattice constant, so as to effectively improve interface characteristics of InGaP and SiGe materials.

Claims

1. A high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor, wherein the bipolar transistor is selected from an N-type doped single crystal Si substrate with a crystal orientation (001); an N-type SiGe layer with gradient Ge composition is epitaxially grown on the single crystal Si substrate, serving as a sub-collector, and N+ doping is performed on a right side region of the SiGe layer; a SiO.sub.2 layer with a thickness of 1-2 microns is deposited on a surface of the SiGe layer to define a position of an active area; an N-type In.sub.1-xGa.sub.xP layer serving as a collector, a P-type SiGe layer serving as a base, and an intrinsic Si cap layer are sequentially and epitaxially grown in the active area; a nitride layer and an oxide layer are sequentially deposited on the surfaces of the SiO.sub.2 layer with the thickness of 1-2 microns and the intrinsic Si cap layer and are etched, the oxide layer is re-deposited on the surfaces of the etched nitride layer and oxide layer and etched, to form a sidewall oxide layer; a polysilicon is deposited on the sidewall oxide layer as an emitter; the oxide layer is epitaxially grown on a surface of the device obtained as a surface covering oxide layer of the emitter, the surface covering oxide layer and the oxide layer on the nitride layer are etched, and the nitride layer is etched, the polysilicon layer are selectively and epitaxially grown at a position where the nitride is located and etched, serving as an extrinsic base; a sidewall oxide layer of an extrinsic base is deposited; the emitter, the extrinsic base and the sub-collector are etched respectively, and a metal silicide is deposited to form an emitter contact, a base contact and a collector contact.

2. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 1, wherein a N-type In.sub.1-xGa.sub.xP is used as a material of the collector of a SiGe-HBT, and a composition molar ratio x of In and Ga is selected, that is 0≤x≤1, so that the materials of the collector and the sub-collector SiGe have the same lattice constant.

3. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 1, wherein a SiGe/Si structure heteroepitaxial N-type In.sub.1-xGa.sub.xP material is used as the collector.

4. The high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 1, wherein a method for employing MBE in the active area, by which the N-type In.sub.1-xGa.sub.xP layer serving as a collector, the P-type SiGe layer, and the intrinsic Si cap layer are sequentially and epitaxially grown.

5. A method for preparing a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor, comprising following steps: step 1, selecting an initial material with monocrystalline silicon doping concentration 10.sup.15 cm.sup.−3 and crystal orientation (001) as a substrate; step 2, depositing an SiO.sub.2 layer with a thickness of 50 nanometers on an N-type doped single crystal Si substrate; step 3, photoetching the SiO.sub.2 layer by using a mask 1, and then selectively epitaxially growing an N-type SiGe layer with a gradient Ge composition as a sub-collector of the heterojunction bipolar transistor, and the Ge composition on a top layer of the N-type SiGe layer is 20%; step 4, by using a mask 2, performing ion implantation on a right side of the N-type SiGe layer in step 3 to form an N+ area; step 5, depositing an SiO.sub.2 layer with the thickness of 1-2 microns on an upper surface of the device obtained in step 4; step 6, by using a mask 3, etching and defining a position of the active area, epitaxially growing the N-type In.sub.1-xGa.sub.xP layer as the collector, the P-type base SiGe layer and the intrinsic Si cap layer selectively and sequentially; step 7, sequentially depositing a nitride layer and an oxide layer on the surface of the device formed in step 6, and etching the nitride layer and the oxide layer by using a mask 4 and a mask 5; step 8, depositing the oxide layer on the surface of the device formed in step 7, and etching the oxide layer by using a mask 6 to form an EB sidewall oxide layer; step 9, epitaxially growing an N+ polysilicon emitter on the oxide layer selectively, and forming an N+ emitter after CMP; step 10, epitaxially growing an oxide layer on the surface of the device obtained in step 9 as a surface covering layer of the emitter; step 11, etching the nitride layer in step 7, and then etching the oxide layer in step 8 by using a mask 7; step 12, selectively depositing a P+ polysilicon layer on the upper surface of the device obtained in step 11, and etching the P+ polysilicon layer by using a mask 8 to form an extrinsic base of the device; step 13, depositing an oxide layer on the upper surface of the device obtained in step 12, and etching the oxide layer deposited in this step by using a mask 9 to form a sidewall oxide layer; step 14, etching the emitter, the extrinsic base and the sub-collector, and depositing a silicide to form a metal contact, thereby forming a collector contact, a base contact and an emitter contact.

6. The method for preparing the high voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 5, wherein in step 6, using a method of MBE in the active area to perform selectively epitaxially growing.

7. The method for preparing the high voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 5, wherein in step 6, a composition molar ratio of In and Ga is appropriately selected so that materials of the collector and the sub-collector have the same lattice constant.

8. The method for preparing the high voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor according to claim 5, wherein in step 6, using a SiGe/Si structure heteroepitaxial N-type In.sub.1-xGa.sub.xP material as a collector.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a schematic sectional view of an embodiment of the present disclosure;

(2) FIG. 2 is a schematic view of an N-type doped single crystal Si substrate in an embodiment of the present disclosure;

(3) FIG. 3 is a schematic view of the device obtained in step 2 in an embodiment of the present disclosure;

(4) FIG. 4 is a schematic view of the device obtained in step 3 in an embodiment of the present disclosure;

(5) FIG. 5 is a schematic view of the device obtained in step 4 in an embodiment of the present disclosure;

(6) FIG. 6 is a schematic view of the device obtained in step 5 in an embodiment of the present disclosure;

(7) FIG. 7 is a schematic view of the device obtained in step 6 in an embodiment of the present disclosure;

(8) FIG. 8 is a schematic view of the device obtained in step 7 in an embodiment of the present disclosure;

(9) FIG. 9 is a schematic view of a device obtained after steps 8 and 9 in an embodiment of the present disclosure;

(10) FIG. 10 is a schematic view of the device obtained in step 10 in an embodiment of the present disclosure;

(11) FIG. 11 is a schematic view of the device obtained in step 11 in an embodiment of the present disclosure;

(12) FIG. 12 is a schematic view of the device obtained in step 12 in an embodiment of the present disclosure;

(13) FIG. 13 is a schematic view of the device obtained in step 13 in an embodiment of the present disclosure.

(14) Reference numbers are listed as follows: 100 N doped single crystal Si substrate, 101 SiO.sub.2 layer, 102 SiGe sub-collector, 103 N+ doped area, 104 thick SiO2 layer, 105 InGaP collector, 106 P-type base SiGe layer, 107 Si cap layer, 108 nitride layer, 109 oxide layer, 110 sidewall oxide layer, 111 N+ emitter, 112 surface covering oxide layer, 113 etched oxide layer, 114 extrinsic base, 115 sidewall oxide layer, 116 emitter contact, 117 base contact, and 118 collector contact.

DETAILED DESCRIPTION

(15) Hereinafter, the embodiments of the present disclosure will be described with reference to the drawings.

(16) As shown in FIG. 1, a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor of the present disclosure is provided. The bipolar transistor is selected from an N-type doped single crystal Si substrate with a crystal orientation (001); an N-type SiGe layer with gradient Ge composition is epitaxially grown on the substrate, serving as a sub-collector area, and N+ doping is performed on a right side region; a SiO.sub.2 layer with a thickness of 1-2 microns is deposited on a surface of the SiGe layer to define a position of an active area; an N-type In.sub.1-xGa.sub.xP layer, a P-type SiGe layer, and an intrinsic Si cap layer are sequentially and epitaxially grown in the active area by using a method of MBE; a nitride layer, an oxide layer and a sidewall oxide layer are sequentially deposited on the surfaces of the device, a polysilicon is deposited on the sidewall oxide layer as an emitter area; the nitride is etched, and further the polysilicon layer are selectively and epitaxially grown, serving as an extrinsic base; a sidewall oxide layer of an extrinsic base is deposited; and finally, the emitter, the extrinsic base and the sub-collector are etched respectively to form an emitter contact, a base contact and a collector contact.

(17) A method for preparing a high-voltage terahertz strained SiGe/InGaP heterojunction bipolar transistor, the method includes following steps of:

(18) step 1, providing an N-type doped single crystal Si substrate 100, as shown in FIG. 2; selecting an initial material with monocrystalline silicon doping concentration 10.sup.15 cm.sup.−3 and crystal orientation (001) as a substrate;

(19) step 2, depositing an SiO.sub.2 layer 101 on the N-type doped single crystal Si substrate 100, as shown in FIG. 3;

(20) step 3, photoetching the SiO.sub.2 layer by using a mask 1, and then selectively epitaxially growing an N-type SiGe layer with a gradient Ge composition, in which the Ge composition on the top layer is 20%. The layer is used as a SiGe sub-collector 102 of the heterojunction bipolar transistor

(21) step 4, by using a mask 2, performing ion implantation on a right side of the SiGe layer to form an N+ doping area 103 for reducing a contact resistance of the controller electrode, as shown in FIG. 5;

(22) step 5, depositing an SiO.sub.2 layer 104, as shown in FIG. 6;

(23) step 6, by using a mask 3, etching and defining a position of the active area, and then by using a MBE technology, epitaxially growing the N-type InGaP layer as an InGaP collector 105, the P-type base SiGe layer 106 and the intrinsic Si cap layer 107 selectively and sequentially, as shown in FIG. 7;

(24) step 7, sequentially depositing a nitride layer 108 and an oxide layer 109 on the surface of the device formed in step 6, and etching the nitride layer 108 and the oxide layer 109 by using a mask 4 and a mask 5, as shown in FIG. 8;

(25) step 8, depositing the oxide layer on the surface of the device formed in step 7, and etching the oxide layer by using a mask 6 to form an EB sidewall oxide layer 110, as shown in FIG. 9;

(26) step 9, epitaxially growing an N+ polysilicon emitter on the oxide layer selectively, and forming an N+ emitter 111 as shown in FIG. 9 after CMP;

(27) step 10, epitaxially growing an oxide layer on the upper surface of the device obtained in step 9 as a surface covering layer 112 of the emitter;

(28) step 11, etching the nitride layer 108, and then etching the oxide layer 109 and the surface covering oxide layer 112 by using a mask 7, wherein the etched structure is the etched oxide layer 113, as shown in FIG. 11;

(29) step 12, selectively depositing a P+ polysilicon layer, and etching the P+ polysilicon layer by using a mask 8 to form an extrinsic base 114 of the device, as shown in FIG. 12;

(30) step 13, depositing an oxide layer, and etching the oxide layer by using a mask 9 to form a sidewall oxide layer 115, as shown in FIG. 13;

(31) step 14, etching the N+ emitter 111, the extrinsic base and the sub-collector, and depositing a silicide to form a metal contact, thereby forming a collector contact 118, a base contact 117 and an emitter contact 116, as shown in FIG. 1.

(32) The above-mentioned embodiments are merely described in the preferred implementations of the present disclosure, and do not limit the scope of the present disclosure. Various modifications and improvements made by those skilled in the art to the technical solution of the present disclosure without departing from the spirit of the present disclosure should fall within the scope of the present disclosure.