SEMICONDUCTOR STORING APPARATUS AND FLASH MEMORY OPERATION METHOD

Abstract

A flash memory capable of automatically releasing a deep power-down mode is provided. The flash memory includes: a standard command interface (I/F) circuit and a deep power-down mode (DPD) controller, operating through an external power voltage; and an internal circuit, operating through internal voltages supplied from voltage supply nodes. The DPD controller detects whether the flash memory is in the deep power-down mode when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode in the case where the deep power-down mode is detected. The standard command is executed after the internal circuit is recovered.

Claims

1. A flash memory operation method, comprising: a step of detecting whether a flash memory is in a deep power-down mode blocking power supply to a specific circuit when a standard command comprising reading, programming, or erasing is inputted; a step of releasing the deep power-down mode in a case where the deep power-down mode is detected; and a step of executing the standard command after the specific circuit is restored.

2. The flash memory operation method according to claim 1, wherein in a case where the deep power-down mode is not detected, the inputted standard command is executed without releasing the deep power-down mode.

3. The flash memory operation method according to claim 1, wherein the step of releasing restores the specific circuit selected according to a type of the standard command.

4. The flash memory operation method according to claim 1, wherein the step of releasing comprises: turning on a switching transistor connected between a power voltage and the specific circuit.

5. The flash memory operation method according to claim 1, wherein, the deep power-down mode transitions from a stand-by mode and further reduces power consumption in the stand-by mode.

6. A semiconductor storing apparatus, comprising: a peripheral circuit; a detection component, for detecting whether a flash memory is in a deep power-down mode blocking power supply to one or more specific circuits of the peripheral circuit when a standard command comprising reading, programming, or erasing is inputted from an outside; a release component, for releasing the deep power-down mode in a case where the deep power-down mode is detected; and an execution component, for executing the standard command after the specific circuit is restored.

7. The semiconductor storing apparatus according to claim 6, wherein in a case where the deep power-down mode is not detected, the standard command is executed without releasing the deep power-down mode through the release component.

8. The semiconductor storing apparatus according to claim 6, wherein, the release component restores the specific circuit selected according to a type of the standard command.

9. The semiconductor storing apparatus according to claim 6, wherein, the release component comprises a plurality of switching transistors respectively connected between an external power voltage and a plurality of specific circuits, and the release component turns on any one of the plurality of switching transistors.

10. The semiconductor storing apparatus according to claim 6, wherein the semiconductor storing apparatus is a flash memory.

11. The semiconductor storing apparatus according to claim 7, wherein the semiconductor storing apparatus is a flash memory.

12. The semiconductor storing apparatus according to claim 8, wherein the semiconductor storing apparatus is a flash memory.

13. The semiconductor storing apparatus according to claim 9, wherein the semiconductor storing apparatus is a flash memory.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG. 1A is a diagram showing an example of an operation waveform when a conventional flash memory transitions to a deep power-down mode (DPD) mode.

[0019] FIG. 1B is a diagram showing an example of an operation waveform when the conventional flash memory is released from the DPD mode.

[0020] FIG. 2 is a diagram showing an internal structure of the conventional flash memory.

[0021] FIG. 3 is a diagram showing an internal structure of a flash memory according to an embodiment of the disclosure.

[0022] FIG. 4 is a flowchart showing a release sequence of a DPD mode according to an embodiment of the disclosure.

[0023] FIG. 5 is a table showing relationships between standard commands and voltage supply nodes and restoration times of recovery according to another embodiment of the disclosure.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

[0024] The semiconductor storing apparatus of the disclosure is not particularly limited, and is implemented as, for example, a Not AND (NAND) or a Not OR (NOR) flash memory.

[0025] Next, the embodiments of the disclosure will be described in detail with reference to the drawings. FIG. 3 is a diagram showing a schematic internal structure of a NAND flash memory according to an embodiment of the disclosure. A flash memory 100 includes: a standard command interface (I/F) circuit 110 for accepting a standard command, a deep power-down mode (DPD) controller 120 for controlling the transition to a DPD mode, the release of the DPD mode, etc., a memory cell array 130, a row decoder 140, a page buffer/readout circuit 150, and internal circuits such as a peripheral circuit 160, a peripheral circuit 170, a high voltage circuit 180, etc.

[0026] The flash memory 100 of the embodiment can operate in a plurality of power consumption modes. An active mode does not limit power consumption and executes standard commands (such as reading, programming, erasing), etc. in full specifications. A stand-by mode operates the internal circuit according to the requirement of the specified power consumption while executing the operation in response to the inputted standard command, etc. when not in the active mode. In the stand-by mode, for example, the charge pump of the high voltage circuit is stopped or the internal supply voltage is reduced. In order to further reduce power consumption in the stand-by mode, the DPD mode blocks power supply to a specific circuit in the stand-by mode.

[0027] The standard command I/F circuit 110 and the DPD controller 120 directly operate using an external power voltage VCC (for example, 3.3V), that is, the standard command I/F circuit 110 and the DPD controller 120 may operate in the stand-by mode and the DPD mode. The standard command I/F circuit 110 is an interface circuit for externally accepting a standard command prepared in advance for a standard operation of a flash memory. The standard commands are, for example, commands for reading, programming, erasing, etc. The standard command I/F circuit 110 includes a complementary metal oxide semiconductor (CMOS) logic device for decoding the inputted standard command, and a decode result DEC is provided to the DPD controller 120 and the peripheral circuit 160 (including a controller, a state machine, etc. used to control the operation of the standard command).

[0028] The DPD controller 120 controls the transition from the stand-by mode to the DPD mode and the release of the DPD mode. A positive channel metal oxide semiconductor (PMOS) transistor P1 is connected between the external power voltage VCC and a voltage supply node INTVDD1, and a PMOS transistor P2 is connected between the external power voltage VCC and a voltage supply node INTVDD2. At the voltage supply node INTVDD1, the row decoder 140, the page buffer/readout circuit 150, the peripheral circuit 160, and the high voltage circuit 180 are connected, and at the voltage supply node INTVDD2, the peripheral circuit 170 is connected.

[0029] The DPD controller 120 generates the L-level DPD enable signal DPDEN1 and DPD enable signal DPDEN2 in the active mode and the stand-by mode to turn on the transistor P1 and the transistor P2, and supplies the external power voltage VCC to the voltage supply node INTVDD1 and the voltage supply node INTVDD2. In addition, the DPD controller 120 in the DPD mode transitions the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 to H-level, sets the transistor P1 and the transistor P2 as not turned on, and blocks voltage supply from the external power voltage VCC to the voltage supply node INTVDD1 and the voltage supply node INTVDD2. For example, the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 may be transitioned to H-level at different timings according to the elapsed time since the time point of transitioning to the stand-by mode.

[0030] The method for transitioning from the stand-by mode to the DPD mode is not particularly limited. In a certain form, the DPD controller 120 does not input a command for transitioning to the DPD mode from the user, but automatically transitions to the DPD mode in response to a signal from the peripheral circuit 160 (including a controller for controlling the operation of the flash memory). For example, if a signal indicating the transition to the stand-by mode is provided from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures time from the time point indicating the transition to the stand-by mode, transitions to the DPD mode when the duration of the stand-by mode exceeds a certain time to transition the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 to H-level, and blocks power supply from the external power voltage VCC. In addition, in another form, the DPD controller 120 may also transition to the DPD mode in response to the inputted command for transitioning to the DPD mode from the user.

[0031] Regarding the method for releasing the DPD mode, in a conventional flash memory, it is necessary to input a dedicated command for releasing the DPD mode from the outside. However, in the embodiment, the DPD mode is automatically released without inputting such a dedicated command. The details of the release function will be described later, but if the standard command I/F circuit 110 receives the standard command in the DPD mode, the DPD controller 120 releases the DPD mode in response to the standard command, and the standard command is seamlessly executed after the time required for the restoration of the DPD mode has elapsed.

[0032] The DPD controller 120 of the embodiment may be constructed using a hardware and/or a software, which may, for example, include a microcomputer, a state machine, a logic device, etc.

[0033] The memory cell array 130 contains a plurality of blocks, and each block contains a plurality of NAND strings. The NAND strings may be two-dimensionally formed on a substrate or three-dimensionally formed along a vertical direction from the main surface of the substrate. In addition, a memory unit may store binary data or multi-value data.

[0034] The peripheral circuit 160 and the peripheral circuit 170 include, for example, the following parts, etc.: a controller or a state machine, for controlling the operation of the flash memory 100 based on the standard command, etc. received by the standard command I/F circuit 110; or an error checking and correction (ECC) circuit and a column selection circuit, for detecting error and correcting data. The high voltage circuit 180 includes a charge pump circuit, etc., for generating the high voltage required for reading, programming, and erasing. In addition, the flash memory 100 may be installed with a serial peripheral interface (SPI). In the SPI, the control signal (allowing address latching, command latching, etc.) is replaced, and inputted command, address, and data are synchronously identified with a serial clock signal.

[0035] Next, the method for releasing the DPD mode of the flash memory according to the embodiment will be described with reference to the flowchart of FIG. 4. If a standard command (S100) is inputted to a standard command I/F circuit 110, a standard command I/F circuit 110 decodes the standard command and provides a decode result DEC to a DPD controller 120 and a peripheral circuit 160. When receiving the decode result DEC, the DPD controller 120 determines whether the decode result DEC is a DPD mode (S110). In the case where the DPD mode is determined, the DPD controller 120 releases the DPD mode (S120). That is, the DPD controller 120 transitions a DPD enable signal DPDEN1 and a DPD enable signal DPDEN2 from H-level to L-level, sets a transistor P1 and a transistor P2 as turned on, and supplies power from an external power voltage VCC to a voltage supply node INTVDD1 and a voltage supply node INTVDD2. Accordingly, an internal voltage VDD1 is supplied from the voltage supply node INTVDD1 to a row decoder 140, a page buffer/readout circuit 150, and the peripheral circuit 160, and an internal voltage VDD2 is supplied from the voltage supply node INTVDD2 to a peripheral circuit 170. Peripheral circuits 140 to 180 are restored to an operable state at a time T.sub.ST after a period tRES as shown in FIG. 1B.

[0036] When the restoration of the peripheral circuit 140 to the peripheral circuit 180 is completed, the peripheral circuit 160 executes the operation of the standard command based on the decode result DEC from the standard command I/F circuit 110 (S130). The period (tRES) during which the peripheral circuit is restored through releasing the DPD mode is a busy period during which access to the flash memory is prohibited. In the embodiment, the standard command is seamlessly executed after the period tRES.

[0037] On the other hand, in the case where the DPD controller 120 determines that the inputted standard command is not the DPD mode (S110), the DPD is not released (that is, the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 are already at L-level), and the operation of the standard circuit is immediately executed through the peripheral circuit 160 (S130).

[0038] As a specific operation example, if a read, program, or erase command is inputted to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 transitions the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 to L-level to turn on the transistor P1 and the transistor P2 in order to release the DPD mode. Next, the internal circuit is restored during the period tRES shown in FIG. 1B, and reading, programming, or erasing is immediately executed.

[0039] In this way, according to the embodiment, the DPD mode is automatically released in response to the inputted standard command. Therefore, it is not necessary to input a dedicated command for releasing the DPD mode and even a flash memory that does not support the command for releasing the DPD mode can release the DPD mode. Furthermore, for a flash memory that automatically controls the transition from the stand-by mode to the DPD mode (that is, a dedicated command for transitioning to the DPD mode is not required), the user input of all commands related to the DPD mode may be skipped to automatically transition and release the DPD mode.

[0040] Next, another embodiment of the disclosure will be described. In the above embodiment, the DPD controller 120 restores all internal circuits from the DPD mode in response to the inputted standard command. However, in the present embodiment, the restored internal circuit is selected according to the type of the standard command. The table in FIG. 5 shows relationships between standard commands of the present embodiment and voltage supply nodes and restoration (recovery) times of restoration. The standard commands include a status read or an identifier (ID) read in addition to reading, programming, and erasing. The status read is to read whether the flash memory is in a ready state, whether the flash memory is in a write protection mode, whether it is a command in a programming/erasing operation, and the ID read is to read a command for identifying a manufacturer or a product.

[0041] In the case where the standard command is equivalent to the status read or the ID read, the DPD controller 120 only transitions a DPD enable signal DPDEN1 to L-level to turn on a transistor P1, and only recovers a voltage supply node INTVDD1. At this time, only the voltage supply node INTVDD1 is recovered, so the recovery time can be accelerated. On the other hand, in the case where the standard command is equivalent to programming, reading, and erasing, the DPD controller 120 transitions both the DPD enable signal DPDEN1 and a DPD enable signal DPDEN2 to L-level to turn on the transistor P1 and a transistor P2, and recovers the voltage supply node INTVDD1 and a voltage supply node INTVDD2. Here, the recovery time is the standard time.

[0042] In this way, according to the embodiment, the DPD mode may be released with an appropriate recovery time according to the operation content of the standard command, and the standard command may be executed.

[0043] In the embodiments, an example in which the external power voltage VCC is supplied to the voltage supply node INTVDD1 and the voltage supply node INTVDD2 is shown, but other internal voltages may also be supplied to the voltage supply node INTVDD1 and the voltage supply node INTVDD2 without directly supplying from the external power voltage VCC.

[0044] The embodiments of the disclosure are described in details above, but the disclosure is not limited to the specific embodiments, and various modifications and changes may be made within the scope of the disclosure as recited in the claims.