Field Effect Transistor and Method for Manufacturing the Same

Abstract

A gate opening, a plurality of first openings arranged in a gate widthwise direction and having a reed shape, a second opening connecting the adjacent first openings, and a third opening connected to a side away from the arrangement of the first opening at an end of the arrangement are formed in an insulation layer. An ohmic cap layer is etched via the openings to form an asymmetric recess region.

Claims

1.-8. (canceled)

9. A method for manufacturing a field effect transistor, the method comprising: a first step of forming a buffer layer, a channel layer, a barrier layer, a carrier supply layer, and an ohmic cap layer on a semiconductor substrate; a second step of forming a source electrode and a drain electrode separate from each other on the ohmic cap layer; a third step of forming an insulation layer located between the source electrode and the drain electrode on the ohmic cap layer; a fourth step of forming a gate opening located closer to the source electrode than to the drain electrode on the insulation layer; a fifth step of forming a plurality of first openings, a second opening, and a third opening located between the gate opening and the drain electrode in the insulation layer; a sixth step of forming, in regions below the gate opening, the plurality of first openings, the second opening, and the third opening, a recess region in which a part of the ohmic cap layer is removed in directions from the gate opening to the source electrode and to the drain electrode in a plan view by etching the ohmic cap layer using the insulation layer that has the gate opening, the first openings, the second opening, and the third opening as a mask; and a seventh step of forming a gate electrode above the insulation layer, a part of the gate electrode being inserted into the recess region from the gate opening and being Schottky-joined to the barrier layer; wherein the first openings are arranged in a gate widthwise direction with each having a reed shape in a gate lengthwise direction in the plan view; wherein the second opening has the reed shape in the gate widthwise direction in the plan view and is connected to one first opening of the plurality of first openings; wherein the third opening is provided in a region outside of an arrangement of the plurality of first openings arranged in the gate widthwise direction, is connected to another first opening of the plurality of first openings at an end of the arrangement, and is formed in a shape that has a width that gradually broadens from the another first opening at the end of the arrangement in the plan view; and wherein a length of the recess region from the gate electrode to a drain electrode side in the gate lengthwise direction is greater than a length of the recess region from the gate electrode to a source electrode side in the gate lengthwise direction.

10. The method according to claim 9, further comprising: an eighth step of forming an upper insulation layer on the insulation layer after the third step; and a ninth step of forming an upper gate opening in the upper insulation layer so as to be continuous to the gate opening formed in the insulation layer, wherein, in the seventh step, the gate electrode is formed on the upper insulation layer, a part of the gate electrode being inserted into the recess region from the upper gate opening and the gate opening and being Schottky-joined to the barrier layer.

11. A field effect transistor comprising: a buffer layer, a channel layer, a barrier layer, a carrier supply layer, and an ohmic cap layer on a semiconductor substrate; a source electrode and a drain electrode separate from each other on the ohmic cap layer; an insulation layer on the ohmic cap layer between the source electrode and the drain electrode; a gate opening on the insulation layer located closer to the source electrode than to the drain electrode in a plan view; a plurality of first openings, a second opening, and a third opening in the insulation layer between the gate opening and the drain electrode in the plan view; a recess region in which a part of the ohmic cap layer including regions below the gate opening, the first openings, the second opening, and the third opening are removed in directions from the gate opening to the source electrode and to the drain electrode in the plan view; and a gate electrode above the insulation layer, a part of the gate electrode being inserted into the recess region from the gate opening and being Schottky-joined to the barrier layer; wherein the first openings are arranged in a gate widthwise direction with each having a reed shape in a gate lengthwise direction in the plan view; wherein the second opening has the reed shape in the gate widthwise direction in the plan view and is connected to one first opening of the plurality of first openings; the third opening is in a region outside of an arrangement of the plurality of first openings arranged in the gate widthwise direction, is connected to another first opening of the plurality of first openings at an end of the arrangement, and is formed in a shape that has a width that gradually broadens from the another first opening at the end of the arrangement in the plan view; and a length of the recess region from the gate electrode to a drain electrode side in the gate lengthwise direction is greater than a length of the recess region from the gate electrode to a source electrode side in the gate lengthwise direction.

12. The field effect transistor according to claim 11, wherein one pair of the third openings are provided and are connected to the first openings at both ends of the arrangement of the plurality of first openings.

13. The field effect transistor according to claim 11, wherein the second opening is connected to a middle portion of the plurality of first openings in the gate lengthwise direction.

14. The field effect transistor according to claim 11, wherein the second opening is connected to one end of the plurality of first openings in the gate lengthwise direction.

15. The field effect transistor according to claim 11, wherein the second opening is alternately connected to a first end and a second end of the plurality of first openings in the gate lengthwise direction.

16. The field effect transistor according to claim 11, further comprising: an upper insulation layer on the insulation layer; and an upper gate opening in the upper insulation layer that is continuous with the gate opening, wherein a part of the gate electrode is inserted into the recess region from the upper gate opening and the gate opening and is Schottky-joined to the barrier layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1A is a cross-sectional view of a field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0026] FIG. 1B is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0027] FIG. 1C is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0028] FIG. 1D is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0029] FIG. 1E is a plan view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0030] FIG. 1F is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0031] FIG. 1G is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0032] FIG. 1H is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0033] FIG. 1I is a cross-sectional view of the field effect transistor showing the state of a process in the course of manufacturing the field effect transistor according to an embodiment of the present invention.

[0034] FIG. 2 is a cross-sectional view illustrating a configuration of another field effect transistor according to an embodiment of the present invention.

[0035] FIG. 3 is a plan view illustrating a configuration of still another field effect transistor according to an embodiment of the present invention.

[0036] FIG. 4 is a plan view illustrating a configuration of still another field effect transistor according to an embodiment of the present invention.

[0037] FIG. 5 is a plan view illustrating a configuration of still another field effect transistor according to an embodiment of the present invention.

[0038] FIG. 6 is a cross-sectional view illustrating a configuration of a field effect transistor disclosed in Patent Literature 1.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0039] Hereinafter, a method of manufacturing a field effect transistor according to embodiments of the present invention will be described with reference to FIGS. 1A to 1I.

[0040] First, as illustrated in FIG. 1A, a buffer layer 102, a channel layer 103, a barrier layer 104, a carrier supply layer 105, and an ohmic cap layer 106 are formed on a semiconductor substrate 101 including, for example, semi-insulating InP (a first step).

[0041] For example, the buffer layer 102 that includes InAlAs and has a layer thickness of 100 to 300 nm, the channel layer 103 that includes InGaAs and has a layer thickness of 5 to 20 nm, the barrier layer 104 that includes InAlAs and has a layer thickness of 5 to 20 nm, and the ohmic cap layer 106 that includes InGaAs doped with Si in the range of 1×10.sup.19 to 2×10.sup.19 cm.sup.−3 are sequentially stacked on the semiconductor substrate 101 by crystal growth using an organometallic vapor growth method, a molecular beam epitaxial method, or the like. The carrier supply layer 105 doped with Si at 1×10.sup.19 cm.sup.−3 as impurities is formed on the barrier layer 104 by known sheet doping. Here, in the embodiment, a passivation layer 121 that includes InP and has a layer thickness of 2 to 5 nm is formed between the carrier supply layer 105 and the ohmic cap layer 106.

[0042] Subsequently, as illustrated in FIG. 1B, a source electrode 107 and a drain electrode 108 are formed on the ohmic cap layer 106 to be separate from each other (a second step). The source electrode 107 and the drain electrode 108 are formed with a recess formation region 131, where the recess region is to be formed, interposed therebetween. The source electrode 107 and the drain electrode 108 are formed, for example, by depositing Ti/Pt/Au on the ohmic cap layer 106 to form a metal film and patterning the metal film by a known photolithographic technology and etching technology. The source electrode 107 and the drain electrode 108 can be formed also by a known lift-off method. The source electrode 107 and the drain electrode 108 are ohmic-contacted with the ohmic cap layer 106.

[0043] Subsequently, as illustrated in FIG. 1C, an insulation layer 109 is formed on the ohmic cap layer 106 so as to be located between the source electrode 107 and the drain electrode 108 (a third step). For example, the insulation layer 109 that has a layer thickness of 20 to 200 nm is formed by depositing a silicon oxide or a silicon nitride by a known plasma CVD method.

[0044] Subsequently, as illustrated in FIGS. 1D and 1E, a gate opening no is formed in the insulation layer 109 so as to be located closer to the source electrode 107 than to the drain electrode 108 (a fourth step). The gate opening no is disposed within the recess formation region 131 such that a distance from the drain electrode 108 is greater than a distance from the source electrode 107. The gate opening no is a stripe-shaped (reed-shaped) opening along a gate widthwise direction (a normal direction of the paper surface of FIG. 1D).

[0045] First openings 111a, second openings 111b, and third openings 111c are formed between the gate opening no and the drain electrode 108 within the recess formation region 131 of the insulation layer 109 (a fifth step).

[0046] First, the plurality of first openings 111a are arranged in the gate widthwise direction and each have a reed shape along a gate lengthwise direction in a plan view.

[0047] The second openings 111b have a reed shape along the gate widthwise direction in a plan view and are connected to the plurality of first openings. The second openings 111b are connected to the adjacent first openings ma.

[0048] The third openings 111c are provided in regions outside of the arrangement of the plurality of first openings 111a arranged in the gate widthwise direction, are connected to the first openings 111a arranged at ends, and are formed in a shape that has a width that gradually broadens from the first openings 111a arranged at the ends in a plan view. In the embodiment, one pair of third openings 111c are formed and connected to the first openings 111a arranged at both ends, as described above. In the embodiment, the third openings mc and the first openings ma are connected by the second openings nib.

[0049] The gate opening no, the first openings ma, the second openings nib, and the third openings 111c are formed, for example, by a known electron beam lithographic technology and etching technology.

[0050] For example, the plurality of first openings ma can be formed in the same shape. Similarly, for example, the plurality of second openings nib can be formed in the same shape. Two third openings 111c can be formed in the same shape. For example, the plurality of first openings ma can be formed and arranged in parallel in the gate widthwise direction. In the embodiment, for example, nine first openings 111a are formed, but the present invention is not limited thereto. The number of first openings ma can be appropriately determined so that the first openings 111a are fitted in a desired recess shape.

[0051] Subsequently, as illustrated in FIG. 1F, the ohmic cap layer 106 is etched using the insulation layer 109 that has the gate opening no, the first openings ma, the second openings 111b, and the third openings 111c as a mask. Then, a recess region 112 in which a part of the ohmic cap layer 106 is removed in the directions from the gate opening no to the source electrode 108 and to the drain electrode 109 in a plan view is formed in a region below the gate opening no, the first openings ma, the second openings 111b, and the third openings 111c (a sixth step).

[0052] For example, the ohmic cap layer 106 is etched isotropically by pouring an etchant such as a citric acid from the regions of the above-described openings by wet etching using the etchant. Through this etching, the etchant erodes the ohmic cap layer 106 from each opening to form the recess region 112 which is one continuous space by expansion of the etching in a transverse direction. When the passivation layer 121 including InP is formed, InP is hardly etched by a citric-acid-based etchant. Therefore, the passivation layer 121 serves as an etching stopper, and thus the barrier layer 104 can be prevented from being etched.

[0053] In the forming of the above-described recess region 112, the first openings ma, the second openings 111b, and the third openings 111c are formed when viewed in the gate lengthwise direction centering on the gate opening no. Therefore, a space formed from the gate opening no to the drain side is formed to be broader than a space formed from the gate opening no to the source side. In this way, by providing the plurality of first openings ma, the plurality of second openings 111b, and the plurality of third openings 111c, it is possible to form the recess region 112 that is asymmetric centering on the gate opening no without adding a new step.

[0054] The first openings 111a are used to form an asymmetric recess amount with high accuracy. The second openings 111b are used to spread the etchant to each of the first openings 111a equally. The third openings 111c are used to infiltrate the etchant to all the first openings 111a and the second openings 111b efficiently. The third openings 111c can also be formed outside of an outside element region located further outside of the region in which the gate opening no is formed in the gate widthwise direction. The source electrode 107 and the drain electrode 108 may be formed after the recess region 112 is formed and the manufacturing order is within the scope of the transistor manufacturing process examination.

[0055] The first openings 111a are arranged in the gate widthwise direction. An opening length or a formation interval of the first openings 111a in a gate lengthwise direction are determined in accordance with a length (a recess amount) of the recess region 112 in the gate lengthwise direction on the side of the drain electrode 108 and a length (a recess amount) of the recess region 112 in the gate lengthwise direction on the side of the source electrode 107. The recess amount corresponds to an etching amount of the ohmic cap layer 106. This point will be described in more detail with reference to FIGS. 1E and 1f.

[0056] Hereinafter, a length from the gate opening 110 to each of the source and drain sides in the gate lengthwise direction in the recess region 112 is referred to as a “recess width”. For example, a “source-side recess width r.sub.gs” is a length from the gate opening 110 to the source side in the gate lengthwise direction in the recess region 112. A “drain-side recess width r.sub.gd” is a length from the gate opening 110 to the drain side in the gate lengthwise direction in the recess region 112.

[0057] The plurality of first openings 111a are arranged in the gate lengthwise direction between the gate opening 110 and the drain electrode 108. In accordance with an etching amount of the ohmic cap layer 106 for obtaining the target recess width r.sub.gs and recess width r.sub.gd, an opening dimension 1, of the first opening 111a in the gate lengthwise direction, an opening dimension w.sub.r of the first opening 111a in the gate widthwise direction, and an interval s.sub.r between the adjacent first openings 111a are determined.

[0058] The first openings ma are formed in only one line to guarantee the intensity of the insulation layer 109 and are not formed in a plurality of lines as in Patent Literature 1. In principle, the source resistance is preferably as low as possible. Because the depletion due to the recess formation may increase the source resistance, an asymmetric recess formation opening is not formed on the source electrode side. Here, s.sub.g is a distance between the gate opening 110 and the first opening 111a.

[0059] The above described r.sub.gd, r.sub.gs, s.sub.g, and l.sub.r have a relation of “r.sub.gd−r.sub.gs=(sg+lr) . . . (1)”. Here, to avoid the remainder of the recess etching, constraint conditions of “r.sub.gd s.sub.g . . . (2)” and “r.sub.gd≥0.5s.sub.r . . . (3)” are assumed to be satisfied.

[0060] By satisfying the above-described relations, it is possible to form the asymmetric recess structure without depending on an etching rate or an etching time of wet etching necessary to form an asymmetric recess. An etching rate and an etching time T in the formation of the asymmetric recess structure for satisfying the above-described relation and the constraint conditions are determined by “r.sub.gs=a . . . (4).”

[0061] Etching amounts of a source electrode side recess region and a drain electrode side recess region are designed based on balance between an increase effect of parasitic resistance and a reduction effect of parasitic capacitance or drain conductance. For example, a general recess width is in the range of 20 to 200 nm on the source electrode side and is in the range of 50 to 500 nm on the drain electrode side. By forming the recess region within this range, it is possible to sufficiently reduce the drain conductance while sufficiently reducing source resistance. Thus, it is possible to achieve the asymmetric recess structure optimum for improving high-frequency characteristics.

[0062] For example, a design is assumed such that an asymmetric recess width satisfies r.sub.gs=50 nm on the source electrode side and r.sub.gd=200 nm on the drain electrode side. In this condition, the left side of Expression (1) is 150 nm, and thus the first openings 111a are formed in the insulation layer 109 so as to satisfy, for example, s.sub.g=20 nm and l.sub.r=130 nm. For a wet etching time necessary to form the asymmetric recess, for example, when the etching rate is 50 nm/min, an etching time of 60 sec is set in consideration of Expression (3).

[0063] As described above, the second openings nib are connected to the adjacent first openings a and are formed to spread the etchant equally. The second opening nib is formed so as to have an opening width substantially as large as the opening width of the first opening ma. Here, when mechanical strength of the insulation layer 109 is desired to be improved, the width of the second opening 111b can be slimmer than the width of the first opening 111a. For example, the width of the second opening 111b can be set to ⅓ to ½ of the width of the first opening 111a.

[0064] By arranging such that the third opening 111c is in a tapered shape (a trapezoidal shape) in a plan view and has a width on the long side twice to three times as large as the width of the second opening 111b, it is possible to efficiently infiltrate the etchant from the third openings 111c to each of the first openings 111a and the second openings 111b.

[0065] As described above, by using the first openings 111a, the second openings 111b, and the third openings 111c, it is possible to uniformly infiltrate the etchant into the openings and get into the side of the ohmic cap layer 106 from the openings. As a result, it is possible to guarantee the uniformity and reproduction of the asymmetric recess which has been formed.

[0066] Subsequently, as illustrated in FIG. 1G, an upper insulation layer 113 is formed on the insulation layer 109 (an eighth step). For example, the upper insulation layer 113 with a layer thickness of 20 to 200 nm is formed by depositing a silicon oxide or a silicon nitride by a plasma CVD method or the like.

[0067] Subsequently, as illustrated in FIG. 1H, an upper gate opening 111a is formed in the upper insulation layer 113 so as to be continuous to the gate opening no which is formed in the insulation layer 109 (a ninth step). The upper gate opening 113a is formed, for example, by a known electron beam lithographic technology and etching technology. Because the upper gate opening 113a is formed in the upper insulation layer 113, etching is performed to form the upper gate opening 113a such that the upper gate opening 113a penetrates the upper insulation layer 113. Therefore, the minute upper gate opening 113a can be formed.

[0068] Subsequently, a gate electrode 114 is formed (a seventh step). Here, as illustrated in FIG. 1I, the gate electrode 114 is disposed above the insulation layer 109 (disposed on the upper insulation layer 113), a part of the gate electrode 114 being inserted into the recess region 112 from the gate opening 110 and being Schottky-joined to the barrier layer 104. As described above, because a space formed on the drain side from the gate opening 110 is formed to be larger than a space formed on the source side from the gate opening 110, a length of the recess region 112 from the gate electrode 114 to the drain electrode side in the gate lengthwise direction is greater than a length of the recess region from the gate electrode 114 to the source electrode side in the gate lengthwise direction.

[0069] For example, a lift-off mask is formed such that a predetermined region including the gate opening 110 of the upper insulation layer 113 is opened and the other region including the source electrode 107 and the drain electrode 108 is coated. Subsequently, a gate metal material is deposited on the lift-off mask to form a metal film, and then the lift-off mask is removed (lifted off). In accordance with the lift-off method, the gate electrode 114 can be formed. In the above-described formation of the metal film, the metal deposited and getting into the gate opening 110 penetrates the considerably thin passivation layer 121 to be Schottky joined to the desired barrier layer 104 from the gate opening 110.

[0070] As described above, because the minute upper gate opening 113a (the gate opening 110) can be formed, it is possible to obtain the gate electrode 114 that is Schottky-joined and has a minute dimension in the gate lengthwise direction, and thus it is possible to realize good high-frequency characteristics. By forming the upper insulation layer 113 to block the first openings 111a, the second openings 111b, and the third openings 111c, it is possible to prevent the metal for the gate electrode from getting into the recess region 112. Therefore, it is possible to inhibit a reduction of parasitic capacitance or distortion of an electric field distribution.

[0071] It is possible to provide a function of modulating a channel immediately below a Schottky junction by a potential applied to the gate electrode 114 which is Schottky-joined to the barrier layer 104. The size (gate length) or shape of the gate electrode 114 is designed such that parasitic capacitance does not occur in each of the source electrode 107 and the drain electrode 108 and resistance of the entire gate electrode 114 is sufficiently low.

[0072] The gate electrode 114 includes a metal material such as Ni, W, or WSiN that has small thermal diffusion to the semiconductor substrate 101 and a large work function. The metal material can be deposited by a sputtering method, a vacuum evaporation method, an electroless plating method, an electrode plating method, or the like. A length (gate length) of the gate electrode 114 on a contact surface between the gate electrode 114 and the barrier layer 104 is generally in the range of 10 to 100 nm.

[0073] A distance from the end of the gate electrode 114 to the end of the source electrode 107 on the contact surface between the gate electrode 114 and the barrier layer 104 is at least equal to or greater than the recess width on the source side. A distance from the gate electrode 114 to the end of the drain electrode 108 is at least equal to or greater than the recess width of the drain side. In particular, to improve output characteristics of the transistor, it is also possible to set the distance from the gate electrode 114 to the end of the drain electrode 108 to be longer than the distance from the gate electrode 114 to the end of the source electrode 107.

[0074] Incidentally, as described above, after the first openings ma, the second openings 111b, and the third openings 111c are formed in the insulation layer 109, the upper insulation layer 113 is formed, but the present invention is not limited thereto. For example, after the insulation layer 109 is formed and the upper insulation layer 113 is continuously formed, the gate opening no, the first openings ma, the second openings 111b, and the third openings 111c can also be formed. For example, the first openings ma, the second openings 111b, and the third openings 111c are formed to penetrate the upper insulation layer 113 and the insulation layer 109, the recess region 112 is subsequently formed, and then the gate electrode 114 is formed. In this case, in the formation of the gate electrode 114, a metal layer is formed in the first openings ma, the second openings 111b, and the third openings 111c.

[0075] After the recess region 112 is formed using the insulation layer 109, the gate electrode 114 can also be formed without forming the upper insulation layer 113 (see FIG. 2). Even in this case, in the formation of the gate electrode 114, a metal layer is formed in the first openings ma, the second openings 111b, and the third openings inc. Here, by forming the first openings ma, the second openings 111b, and the third openings 111c so as to have a width w.sub.r, for example, equal to or less than 50 nm, and forming the gate electrode 114 by a sputtering method, it is possible to inhibit the metal from being deposited on the barrier layer 104 or the passivation layer 121 via the first openings ma, the second openings 111b, and the third openings inc.

[0076] As illustrated in FIG. 3, the second openings 111b can also be disposed in the middle portion of the first openings 111a in the gate lengthwise direction.

[0077] As illustrated in FIG. 4, the second opening 111b can also be disposed at one end of the first opening 111a in the gate lengthwise direction. In the example illustrated in FIG. 4, the second opening 111b is disposed at one end of the first opening 111a away from the gate electrode 114. In this configuration, the upper portion of the gate electrode 114 does not interfere with the second openings 111b and the third openings inc. Then, the gate electrode 114 can be disposed in a portion in which an area ratio is large and mechanical strength is high in the insulation layer 109, and thus it is possible to improve a yield of a device manufacturing.

[0078] As illustrated in FIG. 5, the second openings 111b can also be disposed alternately at one end and the other end of the first openings 111a in the gate lengthwise direction. In this case, an opening in which the first openings 111a and the second openings 111b are continuous is formed in a meandering shape. With this structure, it is possible to reduce occurrence of mechanical stress and bias in the insulation layer 109, and thus it is possible to improve a yield of device manufacturing.

[0079] As described above, according to embodiments of the present invention, the plurality of reed-shaped first openings arranged in the gate widthwise direction, the second openings connected to the adjacent first openings, and the third openings connected to a side away from the arrangement of the first openings at the end of the arrangement are used. Therefore, it is possible to form the asymmetric recess structure of the field effect transistor with more freedom of design and with better uniformity.

[0080] It should be apparent to those skilled in the art that the present invention is not limited to the above-described embodiments and many modifications and combinations can be made within the technical ideas of the present invention.

REFERENCE SIGNS LIST

[0081] 101 Semiconductor substrate [0082] 102 Buffer layer [0083] 103 Channel layer [0084] 104 Barrier layer [0085] 105 Carrier supply layer [0086] 106 Ohmic cap layer [0087] 107 Source electrode [0088] 108 Drain electrode [0089] 109 Insulation layer [0090] 110 Gate opening [0091] 111a First opening [0092] 111b Second opening [0093] 111c Third opening [0094] 112 Recess region [0095] 113 Upper insulation layer [0096] 113a Upper gate opening [0097] 114 Gate electrode [0098] 121 Passivation layer [0099] 131 Recess formation region