Alignment-Tolerant Gallium Oxide Device

Abstract

A gallium oxide field effect transistor that is built on a base layer. A doped gallium oxide channel layer is disposed on top of the base layer, and a dielectric barrier layer is disposed on top of the gallium oxide channel layer. Source contacts and drain contacts are disposed on top of the dielectric barrier layer, with one each of the drain contacts disposed in an interdigitated manner between one each of the source contacts. The interdigitated source contacts and drain contacts thereby define channels between them, where alternating ones of the channels are defined as odd channels, with even channels disposed therebetween. Gate contacts are disposed on top of the dielectric barrier layer in only one of the odd channels and the even channels.

Claims

1. An electronic circuit including a gallium oxide power field effect transistor (FET), the gallium oxide field effect transistor comprising: a base layer; a doped gallium oxide channel layer disposed on top of the base layer; a dielectric barrier layer disposed on top of the gallium oxide channel layer, wherein a portion of the dielectric layer is altered for providing a source contact or a drain contact; the source contacts disposed on top of the altered dielectric barrier layer; the drain contacts disposed on top of the altered dielectric barrier layer, with one each of the drain contacts disposed in an interdigitated manner between adjacent ones of the source contacts such that channels are defined as odd channels and with even channels disposed therebetween; and gate contacts disposed on top of the dielectric barrier layer in of the odd channels or the even channels while the even channels or the odd channels without gate contacts are electrically insulated, wherein misalignment of the gate contacts in the odd channels between source contacts and the drain contacts causes odd channels to turn on at a rate and voltage that differs from a turn on rate and voltage resulting from misalignment of the gate contacts in the event channels between drain contacts and source contacts and wherein having removing the gate contacts from the odd channels or the even channels provides uniform turn on rate and voltage.

2. The electronic circuit of claim 1, wherein the base layer has a thickness of between about 1,000 angstroms and about 1 millimeter.

3. The electronic circuit of claim 1, wherein the doped gallium oxide channel layer has a thickness of between about 10 angstroms and about 2,000 angstroms.

4. The electronic circuit of claim 1, wherein the dielectric barrier layer has a thickness of between about 10 angstroms and about 500 angstroms.

5. The electronic circuit of claim 1, wherein the channels have a length of between about 500 nanometers and about 10,000 nanometers.

6. The electronic circuit of claim 1, wherein the doped gallium oxide channel layer is n-doped.

7. A method for fabricating a gallium oxide power field effect transistor (FET), the method comprising the steps of: forming a base layer; forming a doped gallium oxide channel layer disposed on top of the base layer; forming a dielectric barrier layer disposed on top of the gallium oxide channel layer; altering a portion of the dielectric layer; forming source contacts and drain contacts on top of the altered portion of the dielectric barrier layer such that the drain contacts are disposed in an interdigitated manner between adjacent ones of the source contacts such that channels are defined between the interdigitated drain contacts and source contacts, where alternating ones of the channels are defined as odd channels and with even channels disposed therebetween; forming gate contacts in only one of the odd channels and the even channels.

8. The method of claim 7, wherein forming each of the source contacts, the drain contacts, and the gate contacts is accomplished at least in part by electron beam lithography, optical lithography, evaporation, sputtering, or a combination thereof.

10. The method of claim 7, wherein forming the doped gallium oxide channel layer is accomplished by ion implantation.

11. The method of claim 7, wherein forming the dielectric barrier layer is accomplished by HVPE, MO-CVD, CVD, mist-CVD, or a combination thereof.

12. The method of claim 7, wherein the base layer is formed with a thickness of between about 1,000 angstroms and about 1 millimeter.

13. The method of claim 7, wherein the doped gallium oxide channel layer is formed with a thickness of between about 10 angstroms and about 2,000 angstroms.

14. The method of claim 7, wherein the dielectric barrier layer is formed with a thickness of between about 10 angstroms and about 500 angstroms.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein:

[0024] FIG. 1 depicts a simplified top plan view of a prior art design of a field effect transistor, for comparison purposes.

[0025] FIG. 2A depicts a simplified cross-sectional view of a properly aligned prior art design of field effect transistor.

[0026] FIG. 2B depicts a simplified cross-sectional view of an improperly aligned prior art design of field effect transistor.

[0027] FIG. 3 depicts a simplified top plan view of a field effect transistor according to an embodiment of the present invention.

[0028] FIG. 4A depicts a simplified cross-sectional view of a properly aligned field effect transistor according to an embodiment of the present invention.

[0029] FIG. 4B depicts a simplified cross-sectional view of an improperly aligned field effect transistor according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0030] With reference now to FIG. 3, there is depicted a FET 300 that has been modified according an embodiment of the present invention. In the embodiment depicted, the modification is to remove the gates 104 that were disposed such that the drains 108 were on the left of the gate 104 and the sources 102 were on the right of the gate 104. What remains is a FET 300 where the gates 104 are only disposed such that the sources 102 are on the immediate left of the gate 104 and the drains 108 are only on the immediate right of the gate 104.

[0031] It is appreciated that in other embodiments the removal of such gates 104 will allow further modification to the FET 300, such as the removal of the source 102 on the far right of FIG. 3. However, no such other modifications are shown in FIG. 3, so that the difference in the placement of the gates 104 can be more readily identified. It is also appreciated that the gates 104 could have been removed such that the sources 102 are on the immediate right of the gate 104 and the drains 108 are only on the immediate left of the gate 104.

[0032] With reference now to FIG. 4A, there is depicted a FET 300 according to an embodiment of the present invention, where the gates 104 have been properly aligned. As with the prior art FET 100, the spacing 114a between the gates 104 and the sources 102 and between the gates 104 and the drains 108 is substantially equal. In such a case, none of the channels 106 disposed underneath the gates 104 will turn on any earlier than any of the other channels 106.

[0033] However, as depicted in FIG. 4B, there is some misalignment of the gates 104 relative to the sources 102 and the drains 108. In this particular embodiment, the gates 104 have been misaligned such that the length 114b between the sources 102 and the gates 104 is shorter than the length 114c between the drains 108 and the gates 104. Notice, however, that the length 114b to the gates 104 is the same for all of the sources 102. This would be true regardless of the direction of misalignment of the gates 104—or in other words, regardless of whether the misalignment created an increase 114c or a decrease 114b in the length between the gate 104 and the source 102. Thus, none of the channels 106 will turn on any earlier than any of the other channels 106, and no hot spots will form.

[0034] As introduced above, while various embodiments of this invention can be applied to any FET technology, it is especially applicable to those technologies that have very small dimensions. For example, at the present time, gallium oxide technology has small dimensions, and so gallium oxide would be a good candidate for the application of various embodiments of the present invention. As future technologies evolve with even smaller technologies, various embodiments of the present invention will have increasing applicability and utility.

[0035] The foregoing description of embodiments for this invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiments are chosen and described in an effort to provide illustrations of the principles of the invention and its practical application, and to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.

REFERENCE NUMBER INDEX

[0036] 100 Prior art field effect transistor [0037] 102 Source [0038] 104 Gate [0039] 106 Channel layer [0040] 108 Drain [0041] 110 Dielectric layer [0042] 112 Base layer [0043] 114 Gap [0044] 300 New embodiment of field effect transistor