Abstract
An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.
Claims
1. An integrated circuit package comprising: an encapsulant; a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals; an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and a land grid array provided on a bottom surface of the package, the land grid array comprising: a plurality of package terminals, each package terminal configured to be soldered to a connection; and an opening, wherein the opening is aligned with the integrated waveguide launcher.
2. The integrated circuit package of claim 1, wherein the opening is provided in one of the package terminals.
3. The integrated circuit package of claim 1, wherein the land grid array comprises a metal pad and the opening is provided in the metal pad.
4. The integrated circuit package of claim 1, comprising a shield arranged to reflect radiation from the waveguide launcher towards the waveguide opening.
5. The integrated circuit package of claim 4, wherein the shield comprises a layer of silicon, or epoxy, or PCB laminate.
6. The integrated circuit package of claim 4, wherein the shield is a periodically structured shield, or wherein the shield comprises a back-short.
7. The integrated circuit package of claim 1, comprising a redistribution layer between the semiconductor die and the land grid array, wherein the waveguide launcher is provided in the redistribution layer.
8. The integrated circuit package of claim 7, wherein the redistribution layer comprises a single metal layer.
9. The integrated circuit package of claim 4, comprising a multi-layer laminate between the semiconductor die and the land grid array, wherein the shield is attached by a non-conductive adhesive to the multi-layer laminate.
10. A semiconductor device, comprising: an integrated circuit comprising: an encapsulant; a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals; an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and a land grid array provided on a bottom surface of the package, the land grid array comprising: a plurality of package terminals, each package terminal configured to be soldered to a connection; and an opening, wherein the opening is aligned with the integrated waveguide launcher; and a printed circuit board, PCB, comprising a waveguide, wherein: each package terminal is soldered to the PCB; and the waveguide is aligned with the opening provided in the land grid array.
11. The semiconductor device of claim 10, wherein the waveguide is a dielectric filled waveguide.
12. The semiconductor device of claim 10 or claim 11, wherein the shape of the opening is configured to match the waveguide in the PCB.
13. The semiconductor device of any of claim 10, wherein the PCB comprises a resonant patch antenna configured to match the land grid array to the waveguide.
14. The semiconductor device of claim 10, further comprising a heat sink, wherein the heat sink is in contact with a top surface of the integrated circuit package.
15. The semiconductor device of claim 10, further comprising: an antenna feed network coupled to the PCB; and an antenna array coupled to the antenna feed network.
16. An integrated circuit package comprising: an encapsulant; a semiconductor die in the encapsulant, the semiconductor die comprising a plurality of die terminals; an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals; and a land grid array provided on a bottom surface of the package, the land grid array comprising: a plurality of package terminals, each package terminal configured to be soldered to a connection; and an opening, wherein the opening is aligned with the integrated waveguide launcher and provided in one of the package terminals.
17. The integrated circuit package of claim 16, wherein the land grid array comprises a metal pad and the opening is provided in the metal pad.
18. The integrated circuit package of claim 16, comprising a shield arranged to reflect radiation from the waveguide launcher towards the waveguide opening.
19. The integrated circuit package of claim 18, wherein the shield comprises a layer of silicon, or epoxy, or PCB laminate.
20. The integrated circuit package of claim 16, comprising a redistribution layer between the semiconductor die and the land grid array, wherein the waveguide launcher is provided in the redistribution layer.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0045] Illustrative embodiments of this disclosure will be described hereinafter, by way of example only, with reference to the accompanying drawings in which like reference signs relate to like elements and in which:
[0046] FIG. 1 is a cross-sectional view of a prior art semiconductor device comprising an integrated circuit package, waveguide launcher and PCB;
[0047] FIG. 2 is plan view of the prior art waveguide launcher in FIG. 1;
[0048] FIG. 3 is a cross-sectional view of a prior art semiconductor device comprising an integrated circuit package with an integrated waveguide launcher mounted to a PCB;
[0049] FIG. 4 is a cross-sectional view of semiconductor device according to an embodiment of the disclosure;
[0050] FIG. 5 is a cross-sectional view of semiconductor device comprising a periodically structured shield according to another embodiment of the disclosure;
[0051] FIG. 6 is a cross-sectional view of semiconductor device comprising a back-short according to another embodiment of the disclosure;
[0052] FIG. 7 shows a cross-sectional view of an integrated circuit package comprising a periodically structured shield according to a further embodiment of the present disclosure;
[0053] FIG. 8 shows a cross-sectional view of an integrated circuit package comprising a back-short according to a further embodiment of the present disclosure;
[0054] FIG. 9 shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure;
[0055] FIG. 10 shows a bottom view of an embodiment of a land grid array according to the present disclosure;
[0056] FIG. 11 shows a bottom view of four further embodiments of land grid arrays according to the present disclosure;
[0057] FIG. 12 shows a bottom view of a further embodiment of a land grid array and a close-up portion of a waveguide opening according to the present disclosure; and
[0058] FIG. 13 illustrates the use of patch antennas to match an integrated circuit package to three different PCB substrates.
DETAILED DESCRIPTION
[0059] Embodiments of this disclosure are described in the following with reference to the accompanying drawings. It will be appreciated that the drawings are schematic illustrations and are not drawn to scale.
[0060] FIG. 1 shows a cross-sectional illustration of a prior art semiconductor device. The semiconductor device comprises an integrated circuit package comprising a semiconductor die 2 surrounded by an encapsulant 1. The semiconductor die 2 may equivalently be referred to as a die or chip. A ball grid array comprising solder balls 3 mechanically and electrically connects the die 2 to a waveguide launcher 4. The waveguide launcher 4 is integrated on a substrate 5. The substrate 5 is mounted to a printed circuit board (PCB) 10 comprising integrated waveguides 11. The waveguide launchers 4 are aligned with the waveguides 11. Alternatively, the PCB 10 may be replaced by a slot antenna.
[0061] FIG. 2 shows the waveguide launchers 4 and ball grid array of FIG. 1 in more detail. Section A in FIG. 2 corresponds to section A indicated by the dotted lines in FIG. 1. The waveguide launchers comprise a signal transmission line 6 having a first end and a second end 7. The first end of the signal transmission line 6 is electrically connected to one of the solder balls 3 of the ball grid array on the interface layer 5. The second end 7 of the signal transmission line 6 is radiating into the waveguide 11. The connection from the solder balls 3 to the waveguide 11 using signal transmission line 6, 7 results in significant losses, typically of the order of 2 dB which reduces the SNR.
[0062] FIG. 3 shows another example of a prior art semiconductor device wherein the integrated circuit package comprises a pair of integrated waveguide launchers 4. A ball grid array comprising solder balls 3 mounts the package to a PCB 10. The PCB 10 comprises a pair of integrated waveguides 11 each with a metalized lining 12. The waveguide launchers 4 are aligned with the waveguides 11 in the PCB 10, so as to direct a signal (depicted by the curved lines) through the waveguide 11. In this example, the PCB 10 is mounted to a slot antenna array 65.
[0063] In FIG. 3, the solder balls 3 result in an air gap between the package (or waveguide launchers 4) and the waveguides 11. The air gaps can lead to discontinuities of the surface current of the waveguide, causing mismatch, higher insertion loss and radiation leakage. In addition, the PCB substrate 10 usually consists of mm-wave substrates such as Rogers 3003 which are expensive. The waveguide launcher 4 and the waveguides 11 can also become misaligned which also increases losses.
[0064] An embodiment of a semiconductor device according to the present disclosure is shown in FIG. 4. The integrated circuit package 100 comprises a semiconductor die 2 and integrated waveguide launchers 4 both surrounded by an encapsulant or mold 1. The die 2 is electrically connected to the waveguide launchers 4 by a redistribution layer 13 mounted on a package substrate 6. A bottom surface of the package 100 comprises a land grid array comprising package terminals 14 (shown in more detail in FIGS. 8 to 10) which are electrically connected by solder or solder paste 17 to connections 16 on the PCB 10. The PCB 10 may comprise a low-cost substrate such as FR4.
[0065] The PCB 10 comprises integrated waveguides 11, which may be hollow or filled with a dielectric. As shown, in FIG. 4, there are no air gaps between the waveguide launchers 4 and the waveguides 11. Also, by directly soldering the package terminals 14 to the PCB connections 16 the integrated waveguide launcher 4 cannot become misaligned from the PCB.
[0066] Another embodiment of a semiconductor device according to the present disclosure is shown in FIG. 5. The semiconductor die 2 comprises a plurality of die terminals 21. A redistribution layer 13 is provided between the die 2 and a land grid array on the bottom surface of the package 100. The land grid array comprises package terminals 14 and waveguide openings 27. A plurality of the die terminals 21 are electrically connected to respective package terminals 14 by a metalized structure 15 in the redistribution layer 13.
[0067] The redistribution layer 13 also comprises an integrated waveguide launcher 4 connected to one of the die terminals 21. The die 2 may have single ended terminals or differential terminals. The waveguide launcher 4 converts the die terminal mode to a waveguide mode. The waveguide launcher 4 is arranged such that the electromagnetic radiation emitted is directed towards waveguide openings 27 in the land grid array. The package terminals 14 are soldered 17 to connections 16 on the PCB 10. The PCB 10 comprises an integrated waveguide 11 having a metallic lining 12. The waveguide 11 may be filled with a dielectric material, or it may be hollow. The waveguide 11 is aligned with waveguide openings 27 in the package.
[0068] The package 100 also comprises an integrated shield 30. As shown in FIG. 5, the shield 30 is surrounded by the encapsulant 1 adjacent to the die 2. The shield 30 reflects or partially reflects the electromagnetic radiation emitted by the waveguide launcher 4 towards the waveguide openings 27. This may reduce electromagnetic radiation losses and improve isolation. In this embodiment, the shield 30 is a periodically structured shield and comprises a first layer 31 and periodic structures 32 that act as a surface wave filter. The period structures 32 are made of conductive material, for example copper. The first layer 31 is mounted to a redistribution layer (RDL) 13. The first layer 31 may comprise or consist of silicon, epoxy or PCB laminate, but is not limited to these materials. The first layer 31 may equivalently be referred to as the substrate or shield substrate.
[0069] FIG. 6 shows the semiconductor device of FIG. 5, wherein the shield comprises a back-short 30 rather than a periodically structured shield. In this embodiment, the back-short 30 comprises a first layer 31 and a conductive cover 34. The conductive cover 34 comprises vias 35 which connect the conductive cover 34 to the land grid array, optionally to a ground of the land grid array. In this embodiment an adhesive is not required to mount the first layer 31 to redistribution layer 13. The first layer 31 may comprise or consist of silicon, epoxy or PCB laminate, but is not limited to these materials.
[0070] Another embodiment of an integrated circuit package 100 is shown in FIG. 7. In FIG. 7, the semiconductor die 2 is connected by solder balls 3 to die terminals 21 and to an integrated waveguide launcher 4. It will be appreciated that alternative electrical connections to the solder balls 3 may be used. The die terminals 21 are connected to package terminals 14 on a bottom surface of the package 100 by vias or other electrical connections 15 provided on a multi-layer laminate 13′. The package terminals 14 are provided in a land grid array.
[0071] In FIG. 7, the package 100 comprises a periodically structured shield 30, which is similar to the shield shown in FIG. 5. A plurality of periodic structures 32 made of conductive material are attached to the first layer (or substrate) 31. The first layer (or substrate) 31 may comprise or consist of silicon, epoxy or PCB laminate, but is not limited to these materials. The shield 30 is mounted above the waveguide launcher 4 and to a top surface of the multi-layer laminate 13′ by a non-conductive adhesive 33.
[0072] FIG. 8 shown the package 100 in FIG. 7, wherein the shield comprises a back-short 30 rather than a periodically structured shield. The first layer (or substrate) 31 of the shield comprises a conductive cover 34. The conductive cover 34 is connected to the land grid array (or package terminals 14) by vias 35. The back-short 30 is mounted above the waveguide launcher 4 and to a top surface of the multi-layer laminate 13′ by a non-conductive adhesive 33. In other embodiments, the adhesive 33 may not be provided (as in FIG. 6).
[0073] A further embodiment of a semiconductor device according to the present disclosure is shown in FIG. 9. A heat sink 40 is in contact with a top surface of the package 100. The heat sink 40 is connected to the semiconductor device by a pair of mechanical fixings 42 such as bolts or screws. The mechanical fixings 42 may also add stability and strength to the semiconductor device.
[0074] The integrated circuit package 100 comprises integrated waveguide launchers 4 and is mounted to a PCB 10 by a land grid array 25. The PCB 10 comprises dielectric filled waveguides 11 having a metalized lining 12. The land grid array 25 comprises openings 27 that are aligned with the waveguide launchers 4 and waveguides 11. The PCB 10 comprises a metal layer 50 that connects the PCB 10 to an antenna feed network 60. The antenna feed network 60 is coupled to an antenna array 65. The antenna array 65 may, for example, be a slot antenna array.
[0075] A bottom view of an embodiment of a land grid array 25 is shown in more detail in FIG. 10. The land grid array 25 comprises a plurality of package terminals or AC/DC contact pads 29. Four of the package terminals 29 each comprise an opening 27. In some embodiments, more or less than four openings 27 may be provided. In this embodiment, the openings 27 are rectangular to match a rectangular waveguide. However, it will be appreciated that the shape and size of openings 27 are preferably selected to match the waveguide 11 in the PCB. This matching may prevent the presence of discontinuities in the path taken by electromagnetic radiation, thereby reducing losses.
[0076] FIG. 11 shows four more embodiments of land grid arrays 25 according to the present disclosure. In these embodiments, the waveguide openings 27 are provided in a metal pad 26 rather than in the package terminals 29. The metal pad 26 may be a copper pad. It will be appreciated that although the metal pad 26 is shown as a square shape which is positioned centrally on the land grid array 25, other shapes and positions may be used. As shown, the openings 27 may be circular, square, rectangular, slotted and/or elliptical. The openings 27 may be surrounded by soldermask 28 as shown in the top-right diagram in FIG. 11. The soldermask 28 prevents solder from following into the opening 27 which could potentially create a short circuit.
[0077] As shown in FIG. 12, the openings 27 may be surrounded by a ring 70 of vias or micro-vias 72. The vias 72 may be filled with electrically conductive material. The ring 70 may connect the land grid array 25 to the lead frame or redistribution layer of the package 100. The vias 72 can serve as a barrier to prevent radiation leakage from openings 27, thereby preventing radiation from one opening 27 reaching another opening 27.
[0078] FIG. 13 illustrates the use of resonant patch antennas to match an integrated circuit package 100 to three different PCB substrates 10, 10′ and 10″. Although a package 100 may be designed to match a particular PCB substrate, it may be desired to use the package 100 with a different substrate. Thus, the PCB may need to be matched to the package 100 using a resonant patch. The top row in FIG. 13 shows three simplified cross-sectional diagrams of semiconductor devices, and the bottom row shows a top view of the corresponding PCB.
[0079] In the far-left diagram in FIG. 13, the PCB 10 is made of a similar material to the package substrate, so no impedance matching is required. In the middle diagram, the PCB substrate 10′ is different to the package substrate and so a resonant patch 80′ is inserted into an inner layer of the PCB. It will be appreciated that the patch 80′ could alternatively be placed on the top or bottom of the PCB. In the far-right diagram in FIG. 13, a resonant patch 80″ is placed on the top of the PCB 10″ in order to match the PCB 10″ to the package substrate. This matching may prevent the presence of discontinuities in the path taken by electromagnetic radiation, thereby reducing losses.
[0080] In FIG. 13 a rectangular waveguide and rectangular waveguide is shown. However, it will be appreciated that any shape of waveguide may be used, such as elliptical or circular. The waveguide is preferably matched to the shape of the opening 27 in the land grid array (as described in FIG. 11).
[0081] Accordingly, there has been described an integrated circuit package and a semiconductor device incorporating an integrated circuit package. The integrated circuit package comprises an encapsulant and a semiconductor die (or chip) in the encapsulant. The semiconductor die comprises a plurality of die terminals. A waveguide launcher is also integrated into the package, wherein the integrated waveguide launcher is connected to one of the die terminals.
[0082] A land grid array is provided on a bottom surface of the package, the land grid array comprising a plurality of package terminals, each package terminal configured to be soldered to a connection, and an opening, wherein the opening is aligned with the integrated waveguide launcher. Each package terminal may be soldered to a PCB comprising a waveguide. The waveguide may be aligned with the opening provided in the land grid array.
[0083] Although particular embodiments of this disclosure have been described, it will be appreciated that many modifications, additions and/or substitutions may be made within the scope of the appended claims.
