System and Methods for Ultrasound Imaging with Modularized Frontend and Personal Computer System

Abstract

A modularized ultrasound apparatus utilizes a PC system such as PC case, thermal management subsystem, power supply unit, motherboard, CPU, memory, hard drive, GPU, to build an ultrasound system by inserting frontend modules integrated on PCIe expansion cards as modularized components into the PC system's PCIe expansion subsystem.

Claims

1. An ultrasound imaging apparatus comprising: a frontend subsystem configured to control the operation of a probe connected to said frontend subsystem by transmitting and receiving ultrasound wave into the target of interest, condition and digitize the received signal, and send the digital data into an imaging processor; and a PC system configured to implement the image processor to generate at least one ultrasound image; wherein the frontend subsystem is further configured to have a single or a plurality of frontend module(s) of the form of computer high-speed bus PCIe card(s) which is(are) plugged into a single or a plurality of high-speed PCIe expansion slot(s) of the PC system's PCIe expansion subsystem. wherein said frontend module's PCIe form factor matches PCI slot of said PC system's PCIe expansion subsystem box and secures itself to said PC system's PCIe expansion subsystem box when plugged into the PCIe expansion slot of said PC system.

2. The ultrasound imaging apparatus of claim 1, wherein the frontend module is configured to has a connector sit on the PCIe bracket, wherein said connector is used to connect to a probe outside of the PC case.

3. The ultrasound imaging apparatus of claim 1, wherein the frontend module is configured to have power input, clock and synchronization signal input or output.

4. The ultrasound imaging apparatus of claim 1, wherein the frontend module is configured to have a FPGA to control the transmit and receive of the ultrasound signals as well as sending the ADC data to the CPU or GPU through PCIe connector.

5. The ultrasound imaging apparatus of claim 4, wherein the frontend module is further configured to send per transmit/receive event ADC data to CPU or GPU memory.

6. The ultrasound imaging apparatus of claim 4, wherein the FPGA is a low end FPGA control unit with PCIe IP controller.

7. The ultrasound imaging apparatus of claim 4, wherein the FPGA is further configured to have a Soft CPU implemented on the FPGA to implement: a) transmit signal generation and excitation of a probe; b) receiving signal, conditioning, and ADC sampling; c) coordinating transmit and receive; wherein the FPGA is further configured to have a soft CPU implemented on the FPGA to send ADC sampled data back to the imaging processor.

8. The ultrasound imaging apparatus of claim 7, wherein a dual port data buffer is used to work as a common buffer bridge between these two soft CPUs.

9. The ultrasound imaging apparatus of claim 1, wherein the frontend module is further configured to have an EM shielding structure to protect the sensitive circuit from EM interferences inside PC system's PCIe expansion subsystem box

10. The ultrasound imaging apparatus of claim 9, wherein the EM shielding structure and the PCI bracket are made out of one piece of metal.

11. The ultrasound imaging apparatus of claim 1, wherein the frontend module can be configured as either master or slave; wherein the master frontend module is configured to output clock signal and synchronization signal; wherein the slave frontend module can receive clock signal and synchronization signal.

12. The ultrasound imaging apparatus claim 1, further comprising: a probe adapter module with shielding box wherein the probe adapter connect to the frontend subsystem through the connector on the PCIe bracket of the frontend module; wherein the probe adapter has a probe connector interface which is used to connect to a probe.

13. The ultrasound imaging apparatus claim 1, further comprising: a probe adapter subsystem which has multiple cables and connectors pairs where some cable/connector pair connects to the connector on the frontend module, some cable/connector pair connects to each individual probe, switches are used to selectively connect different probes to the frontend modules.

14. The ultrasound imaging apparatus of claim 1, wherein the image processor subsystem is further configured to have Pre-Allocate buffers in host memory for receiving data from frontend modules during the startup of the PC.

15. The ultrasound imaging apparatus of claim 1, wherein the PC system is configured to have a PSU module; wherein the PSU can use medical grade PSU to meet medical regulations.

16. An ultrasound treatment apparatus comprising: a treatment frontend subsystem configured to control the operation of a probe connected to said frontend subsystem by transmitting ultrasound wave into the target of interest; and a PC system configured to control the frontend subsystem; wherein the frontend subsystem is further configured to have a single or a plurality of Frontend module(s) of the form of computer high-speed bus PCIe card(s) which is(are) plugged into a single or a plurality of high-speed PCIe expansion slot(s) of the PC system's PCIe expansion subsystem. wherein said Frontend module's PCIe form factor matches PCI slot of said PC system's PCIe expansion subsystem box and secures itself to said PC system's PCIe expansion subsystem box when plugged into the PCIe expansion slot of said PC system.

17. An ultrasound treatment as well as imaging apparatus comprising: an imaging frontend subsystem configured to control the operation of a probe connected to said frontend subsystem by transmitting and receiving ultrasound wave into the target of interest, condition and digitize the received signal, and send the digital data into an imaging processor; a treatment frontend subsystem configured to control the operation of a probe connected to said frontend subsystem by transmitting ultrasound wave into the target of interest; and a PC system configured to implement the image processor to generate at least one ultrasound image; wherein the frontend subsystem is further configured to have a single or a plurality of Frontend module(s) of the form of computer high-speed bus PCIe card(s) which is(are) plugged into a single or a plurality of high-speed PCIe expansion slot(s) of the PC system's PCIe expansion subsystem. wherein said Frontend module's PCIe form factor matches PCI slot of said PC system's PCIe expansion subsystem box and secures itself to said PC system's PCIe expansion subsystem box when plugged into the PCIe expansion slot of said PC system.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0022] FIG. 1 illustrates a Frontend PCIe module, according to one embodiment of the present invention.

[0023] FIG. 2 illustrates a completely assembled system, according to one embodiment of the present invention.

[0024] FIG. 3 illustrates a top view diagram of an embodiment of a high channel count module (HCCM).

[0025] FIG. 4 illustrates another completed system with high physical channel count and high computation power, according to one embodiment of the present invention.

[0026] FIG. 5 illustrates PCB design of the frontend PCIe card, according to one embodiment of the present invention.

[0027] FIG. 6 illustrates FPGA frontend control system design block diagram, according to one embodiment of the present invention.

[0028] FIG. 7 illustrates a diagram of the master high channel count module (HCCM)'s clock and synchronization system. A HCCM subsystem configured with multiple frontend PCIe modules interconnected, according to one embodiment of the present invention.

[0029] FIG. 8 illustrates a diagram of the slave high channel count module (HCCM)'s clock and synchronization system.

[0030] FIG. 9 illustrates an embodiment of the probe connector convertor, which connects two Frontend Modules and one ultrasound probe, according to one embodiment of the present invention.

DETAILED DESCRIPTION

[0031] Various embodiments and aspects of the inventions will be described with reference to details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the invention and are not to be construed as limiting the invention. Numerous specific details are described to provide a thorough understanding of various embodiments of the present invention. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present inventions.

[0032] Reference in the specification to “one embodiment” or “an embodiment” or “another embodiment” means that a particular feature, structure, or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment.

[0033] FIG. 1 illustrates diagram of an embodiment of a Frontend Card (Module): transmitter, receiver amplifier, A/D converter, FPGA controller, memory block, Clock circuitry, power regulator, all located on a PCIe card form factor, with a high element count connector 14 exposed outside of the PCIe bracket 13. The PCIe gold finger is shown as 15, Shield boxes for analog and digital circuits are shown as 11 and 12, respectively. The power connector 16 is used to connect to an outside power supply. A group of 5 coax connectors 17 are used for clock signal input/output, synchronous trigger signals input/output. Note that as shown in the figure, the PCI bracket and the shielding box are generated from the same piece of sheet of shielding material. Note that in FIG. 7 below, a Frontend subsystem with multiple Frontend Cards (Modules) are illustrated by inter-connecting these Frontend Cards through these coax connectors.

[0034] FIG. 2 illustrates top view diagram of an embodiment of a completely assembled system for implementing an apparatus of the present disclosure: a complete PC system with two Frontend modules plugged into its motherboard high-speed extension slots. All the standard parts for a PC system are included, such as a case 31, power supply unit (PSU) 41, cooling fans 37 and 38, hard drive 42, motherboard 32, GPU 35, CPU 39, Memory 40, display 46, keyboard 43, trackball 44. Only non existing off-the-shelve components are the two Frontend Modules 33, 34 and the probe connector 36.

[0035] FIG. 3 illustrates a top view diagram of an embodiment of a high channel count module (HCCM) which is implemented by a PCIe extension enclosure 70. In the diagram, there are 8 PCIe Frontend modules are used, 71 to 78. All these Frontend modules are plugged in the PCIe slots on the extension board 81 inside the enclosure 70. An upstream adapter 80 is commonly used to connect the PCIe enclosure system to a Host via PCIe extension cable 82. Such enclosures has a power supply unit 79. A probe connect adaptor/converter 84 is configured to connect to all the Frontend modules at one side, and at the same side, connect to one or multiple probes.

[0036] FIG. 4 illustrates a diagram of an embodiment of a complete high channel count system with one or multiple high channel count modules (HCCM) 51˜54: all the extension enclosures are connected to the PC with high-speed bus 55 such as PCIe or Thunderbolt. Probe connection cables 56 are used to connect probe 57 to each HCCM. A clock and sync signal coax network 58 is used to interconnect all the HCCMs. For example, if each Frontend module has 64 physical channels, each HCCMs will have 256 physical channels, and the 4 HCCMs system in FIG. 4 will have 1024 physical channels. Clearly, a 2048 physical channel system can be build by using 8 HCCMs, etc. A high process power module (HPPM) 63 is illustrated in the system: a PCIe enclosure 63 is used to host 4 GPUs 59˜62. HPPM is connected to the PC with PCIe or thunderbolt cable 64.

[0037] FIG. 5 illustrates the PCB layout of an embodiment of the Frontend card. The PCB 400 is in a PCIe form factor, where the analog circuit 401 such as transmit, receive, high voltage switch, and ADCs are located close to the PCIe bracket 406, which is shown in FIG. 1 as item 13. The digital circuit 402 are located at the opposite side of the PCIe bracket 406. Power connector 403, clock input/output connector 404, and synchronization signal input/output connector 405 are shown. PCIe gold finger 407.

[0038] FIG. 6 illustrates a diagram of an embodiment of the frontend FPGA control system 100 in the Frontend module. A PCIe hardiP 101 is used to connect to the system PCIe bus to receive and send data between Frontend module and CPU or GPU. An analog control system-on-a-programmable-chip (SOPC) 104, also known as soft CPU, can receive configurations of an imaging mode from CPU through PCIe hardIP, and generate each transmit, receive, ADC, and save the data into a buffer 103. An PCIe SOPC 102 is configured to access the common buffer 103, generate DMA sequence and drive the PCIe hardIP 101 in the FPGA to send the DMA data back to CPU/GPU memory through system PCIe bus. The analogy control 104 and the PCIe control 102 are designed to use separate clock domains. As a bridge, the common buffer 103 can be accessed by both Analog control SOPC 104 and PCIe control 102, in a form of dual port memory.

[0039] FIG. 7 illustrates a diagram of an embodiment of the Master HCCM's synchronization system. One Frontend Module 201 is either hardware or software configured as Master and the other three Frontend Model 202˜204 are configured as slaves. The master card will output clock signal 205 which is sent to other slave modules to use. Master card will also generate frame trigger 206 signals which trigger slave cards to start a new frame. Master card will also generate a line trigger 207 which trigger slave cards to start a new transmit and receive event. All the Frontend cards will send their received data individually to the CPU/GPU memory. The off-the-shelve coax cable or Y cable could be used for these interconnection between Master and Slaves.

[0040] FIG. 8 illustrates a diagram of an embodiment of the Slave HCCM's synchronization system. All the Frontend Modules 301˜304 are slave. The clock 305 and trigger signals 306,307 are all from a Master HCCM.

[0041] FIG. 9 illustrates a diagram of an embodiment of the probe adapter (probe connector convertor) 91. two high element count connectors 92 and 93 are used to connect to two Frontend modules. A ultrasound probe connector 94 are located on the other side of the probe connector converter. Proper shielding materials are used to enclose these connectors.