Integrated circuit comprising a junction field effect transistor

Abstract

An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

Claims

1. An integrated circuit, comprising: a semiconductor substrate; and a junction field-effect transistor formed in the semiconductor substrate; wherein the junction field-effect transistor comprises: a drain region and a source region that are spaced from one another in the semiconductor substrate; a channel region in the semiconductor substrate between the drain region and the source region; a gate region in the semiconductor substrate over the channel region and between the drain region and the source region; a first isolating region in the semiconductor substrate having a depth that is deeper than a bottom of the drain region and deeper than a bottom of the channel region, said first isolating region separating the drain region from both the gate region and the channel region; a second isolating region in the semiconductor substrate having a depth that is deeper than a bottom of the source region and deeper than the bottom of the channel region, said second isolating region separating the source region from both the gate region and the channel region; a first connection region in the semiconductor substrate connecting the drain region to the channel region, said first connection region extending along lateral faces and a bottom of the first isolating region; and a second connection region in the semiconductor substrate connecting the source region to the channel region, said second connection region extending along lateral faces and a bottom of the second isolating region.

2. The integrated circuit according to claim 1, wherein the semiconductor substrate has a front face, the source region and the drain region extending downwards from the front face of the semiconductor substrate to depth that is lower than the bottom of the channel region.

3. The integrated circuit according to claim 2, wherein each of the first and second connection regions comprises: a first part in contact with a first lateral face of a corresponding one of the first and second isolating regions and extending vertically into the semiconductor substrate from a lower face of the channel region; a second part in contact with a lower face of the corresponding isolating region and extending horizontally within the semiconductor substrate; and a third part in contact with a second lateral face of the corresponding isolating region and extending vertically into the semiconductor substrate from a lower face of a corresponding one of the source and drain regions.

4. The integrated circuit according to claim 1, wherein the drain region, the source region, the channel region, the first connection region and the second connection region have a first conductivity type, and the gate region has a second conductivity type.

5. The integrated circuit according to claim 1, further comprising at least one bipolar transistor including drift regions having a conductivity type that is same as a conductivity type of the first and second connection regions.

6. The integrated circuit according to claim 5, wherein the bipolar transistor includes a base region extending between third and fourth isolating regions in the semiconductor substrate that have a depth that is deeper than a bottom of the base region, and wherein said drift regions extend along lateral faces and a bottom of the third and fourth isolating regions.

7. The integrated circuit according to claim 6, wherein each drift region comprises: a first part in contact with a first lateral face of a corresponding one of the third and fourth isolating regions and extending vertically into the semiconductor substrate from a lower face of the base region; and a second part in contact with a lower face of the corresponding third and fourth isolating regions and extending horizontally within the semiconductor substrate.

8. The integrated circuit according to claim 1, wherein the first connection region passes under the first isolating region in the semiconductor substrate to connect the drain region to the channel region, and wherein the second connection region passes under the second isolating region in the semiconductor substrate to connect the source region to the channel region.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent on examining the detailed description of completely non-limiting modes of implementation and embodiments and the appended drawings, in which:

(2) FIG. 1 shows an integrated circuit which comprises a junction field-effect transistor (JFET);

(3) FIG. 2 shows a method for manufacturing an integrated circuit such as the one shown in FIG. 1;

(4) FIG. 3 shows an integrated circuit comprising a JFET transistor and a bipolar transistor; and

(5) FIG. 4 shows a method for manufacturing an integrated circuit such as the one shown in FIG. 3.

DETAILED DESCRIPTION

(6) FIG. 1 shows an integrated circuit 10a according to one embodiment, wherein the integrated circuit 10a comprises a junction field-effect transistor, called JFET transistor 11, formed in a semiconductor substrate 12. The semiconductor substrate 12 has a front face 13.

(7) The JFET transistor 11 comprises a drain region 14 and a source region 15 that are spaced from one another. The drain region 14 and the source region 15 have a conductivity of a first type (N or P). In particular, the drain region 14 and the source region 15 each extend downwards from the front face 13 of the semiconductor substrate 12 over a distance of the order of 0.2 μm to 0.3 μm.

(8) The JFET transistor 11 further comprises a gate region 16 between the drain region 14 and the source region 15. The gate region 16 has a conductivity of a second type (P or N) different from the first conductivity type. The gate region 16 extends downwards from the front face 13 of the semiconductor substrate 12 over a distance of the order of 0.2 μm.

(9) The JFET transistor 11 also comprises a channel region 17 between the drain region 14 and the source region 15. The channel region 17 has a conductivity of said first type. The channel region 17 extends downwards from the gate region 16 over a distance of the order of 0.4 μm.

(10) The JFET transistor 11 further comprises, within the substrate 12, a first isolating region 18 separating the drain region 14 from both the gate region 16 and the channel region 17. The first isolating region 18 extends to a depth that is below a bottom of the drain region 14 and channel region 17.

(11) The JFET transistor 11 also comprises, within the substrate 12, a second isolating region 19 separating the source region 15 from both the gate region 16 and the channel region 17. The second isolating region 19 extends to a depth that is below a bottom of the source region 15 and channel region 17.

(12) In particular, the first isolating region 18 and the second isolating region 19 each extend downwards from the front face 13 of the semiconductor substrate 12 over a distance of the order of 1 μm, and thus each region 18, 19 has a depth in the substrate below bottoms of the regions 14, 15 and 17.

(13) The first isolating region 18 and the second isolating region 19 may, for example, comprise silicon dioxide.

(14) More particularly, the channel region 17 and the gate region 16 extend from a first lateral face 18a of the first isolating region 18 to a first lateral face 19a of the second isolating region 19.

(15) The channel region 17 and the gate region 16 thus each have a first longitudinal end against (e.g., in contact with) the first lateral face 18a of the first isolating region 18 and a second longitudinal end against (e.g., in contact with) the first lateral face 19a of the second isolating region 19.

(16) Furthermore, the drain region 14 is arranged against (e.g. in contact with) a second lateral face (side) 18b of the first isolating region 18 opposite the first lateral face 18a of the first isolating region 18.

(17) The source region 15 is arranged against (e.g., in contact with) a second lateral face (side) 19b of the second isolating region 19 opposite the first lateral face 19a of the second isolating region 19.

(18) The JFET transistor 11 also comprises, within the substrate 12, a first connection region 20 connecting the drain region 14 to the channel region 17 while bypassing (e.g., passing along the lateral faces and underneath) the first isolating region 18.

(19) In particular, the first connection region 20 comprises a first part 20a extending vertically into the substrate 12, in contact with said first lateral face 18a of the first isolating region 18, from the channel region 17.

(20) The first connection region 20 comprises a second horizontal part 20b extending horizontally into the substrate 12, in contact with a lower face 18c of the first isolating region 18.

(21) The first connection region 20 also comprises a third part 20c extending vertically into the substrate 12, in contact with the second lateral face 18b of the first isolating region 18, until contacting the drain region 14.

(22) The JFET transistor 11 also comprises, within the substrate 12, a second connection region 21 connecting the source region 15 to the channel region 17 while bypassing (e.g., passing along the lateral faces and underneath) the second isolating region 19.

(23) In particular, the second connection region 21 comprises a first part 21a extending vertically into the substrate 12, in contact with said first lateral face 19a of the second isolating region 19, from the channel region 17.

(24) The second connection region 21 comprises a second horizontal part 21b extending horizontally into the substrate 12, in contact with a lower face of the second isolating region 19.

(25) The second connection region 21 also comprises a third part 21c extending vertically into the substrate 12, in contact with the second lateral face 19b of the second isolating region 19, until contacting the source region 15.

(26) The first connection region 20 makes it possible to connect the drain region 14 to the channel region 17. The second connection region 21 makes it possible to connect the source region 15 to the channel region 17.

(27) The JFET transistor 11 is formed here in an N.sup.−-doped well 22, on top of an N.sup.+-doped buried layer 23 that is itself situated above a P.sup.−-doped carrier substrate 24.

(28) The JFET transistor 11 in this case has a P-type channel. The drain region 14, the source region 15, the channel region 17, the first connection region 20, the second connection region 21 and the carrier substrate 24 of the semiconductor substrate 12 then have P-type conductivity. Furthermore, the gate region 16, the well 22 and the buried layer 23 have N-type conductivity.

(29) In particular, the drain region 14 and the source region 15 have a dopant concentration of the order of 5×10.sup.19 atoms/cm.sup.3 to 2×10.sup.20 atoms/cm.sup.3.

(30) The channel region 17 has a dopant concentration of the order of 10.sup.16 atoms/cm.sup.3.

(31) The gate region 16 has a dopant concentration of the order of 10.sup.17 atoms/cm.sup.3.

(32) The first connection region 20 and the second connection region 21 have a dopant concentration of the order of 10.sup.17 atoms/cm.sup.3.

(33) The well 22 has a dopant concentration of the order of 10.sup.15 atoms/cm.sup.3.

(34) The buried layer 23 has a dopant concentration of the order of 10.sup.19 atoms/cm.sup.3 to 2×10.sup.19 atoms/cm.sup.3.

(35) The carrier substrate 24 has a dopant concentration of the order of 10.sup.19 atoms/cm.sup.3 to 2×10.sup.19 atoms/cm.sup.3.

(36) As a variant, the JFET transistor 11 may have an N-type channel. The drain region 14, the source region 15, the channel region 17, the first connection region 20, the second connection region 21 and the carrier substrate then have N-type conductivity. Furthermore, the gate region 16, the well 22 and the buried layer have P-type conductivity.

(37) Isolating the drain and source regions from the gate region 16 and from the channel region 17 using regions 18 and 19 makes it possible to reduce the stray capacitances between the drain and source regions and the gate region 16. Only surface-diffusing the drain region 14 and the source region 15 also makes it possible to reduce stray capacitances. This reduction in the stray capacitances makes it possible to support high voltages. For example, such a JFET transistor 11 makes it possible to achieve breakdown voltages of the order of 80 volts.

(38) FIG. 2 shows an example of a method for manufacturing an integrated circuit such as the one shown in FIG. 1. In a step 38, the buried layer 23 is produced through dopant implantation into the carrier substrate 24, and then the well 22 is produced through epitaxy.

(39) In step 39, the connection regions 20 and 21 are formed by masking and dopant implantation into the well 22.

(40) The isolating regions 18 and 19 are then formed in step 40, before producing the channel region 17 and producing the drain and source regions 18 and 19 through dopant implantation in step 41.

(41) FIG. 3 shows an integrated circuit 10b according to one embodiment of the invention comprising a JFET transistor 11 as described above and a bipolar transistor 25.

(42) The JFET transistor 11 and the bipolar transistor 25 are formed using the same carrier substrate 26.

(43) The JFET transistor 11 is separated from the bipolar transistor 25 by a shallow trench isolation (STI) 27.

(44) The bipolar transistor 25 is in this case an NPN transistor. As is conventional, it has an intrinsic collector region formed in the well 35, an intrinsic base region 28, an extrinsic base region 30 and an emitter region 29. The bipolar transistor 25 also has drift regions 33 and 34 situated underneath isolation regions 31 and 32, respectively, and contacting the intrinsic base region and the extrinsic base region.

(45) The drift regions 33 and 34 are of the same conductivity type as that of the connection regions 20, 21 of the JFET transistor 11.

(46) As a variant or in combination, the integrated circuit 10b may comprise a JFET transistor 11 with an N-type channel and a PNP bipolar transistor 25.

(47) The method for manufacturing an integrated circuit such as the one shown in FIG. 3 comprises forming a JFET transistor 11 as described above.

(48) The manufacturing method further comprises conventionally forming the bipolar transistor 25.

(49) Moreover, as illustrated in FIG. 4, forming the first connection region 20 and the second connection region 21 and forming the drift regions 33, 34 is carried out in step 39 using the same mask MSK. Furthermore, in this step 39, forming the first connection region 20 and forming the second connection region 21 is advantageously carried out at the same time as forming the drift regions.

(50) Forming the first connection region 20 and forming the second connection region 21 therefore does not require a dedicated additional step. Forming the first connection region 20 and the second connection region 21 is therefore inexpensive.