A semiconductor device with a high on-state current is provided. An oxide semiconductor film; a source electrode and a drain electrode over the oxide semiconductor film; an interlayer insulating film positioned to cover the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the oxide semiconductor film; a barrier insulating film over the oxide semiconductor film; and a gate electrode over the gate insulating film are included. The barrier insulating film is positioned between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are positioned in the opening of the interlayer insulating film. Above the barrier insulating film, the gate insulating film is in contact with the interlayer insulating film.

According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

A method for forming a stacked transistor includes forming a sacrificial cap over a first interconnect of a lower level transistor. The method further includes forming an upper level transistor above the sacrificial cap. The method further includes removing the sacrificial cap to form an opening such that the opening is delimited by the upper level transistor. The method further includes forming a second interconnect in the opening such that the second interconnect is in direct contact with the first interconnect.

Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.

A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

A method of manufacture and structure for a monolithic single chip single crystal device. The method can include forming a first single crystal epitaxial layer overlying the substrate and forming one or more second single crystal epitaxial layers overlying the first single crystal epitaxial layer. The first single crystal epitaxial layer and the one or more second single crystal epitaxial layers can be processed to form one or more active or passive device components. Through this process, the resulting device includes a monolithic epitaxial stack integrating multiple circuit functions.

Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.