THIN FILM TRANSISTOR AND PREPARATION METHOD THEREOF

Abstract

Disclosed is a thin-film transistor including a substrate including a gate electrode formed thereon, a gate insulating film disposed on an entire face of the substrate, a semiconductor layer disposed on an entire face of the gate insulating film, and source and drain electrodes disposed on the semiconductor layer so as to be spaced apart from each other, wherein the semiconductor layer includes cesium tin triiodide (CsSnI.sub.3) or methylammonium tin triiodide (MASnI.sub.3), wherein the semiconductor layer further contains an additive.

Claims

1. A thin-film transistor comprising: a substrate including a gate electrode formed thereon; a gate insulating film disposed on an entire face of the substrate; a semiconductor layer disposed on an entire face of the gate insulating film; and source and drain electrodes disposed on the semiconductor layer so as to be spaced apart from each other, wherein the semiconductor layer includes cesium tin triiodide (CsSnI.sub.3) or methylammonium tin triiodide (MASnI.sub.3), wherein the semiconductor layer further contains an additive.

2. The thin-film transistor of claim 1, wherein the additive is added at a content of 1 mol % to 30 mol % based on the semiconductor layer.

3. The thin-film transistor of claim 2, wherein the additive includes one of SnF.sub.2, SnBr.sub.2, SnI.sub.2, and SnCl.sub.2.

4. The thin-film transistor of claim 2, wherein the additive includes one of PbI.sub.2, InI.sub.2, and SbI.sub.2.

5. The thin-film transistor of claim 2, wherein the additive is a mixture of a first additive and a second additive, wherein the first additive includes one of SnF.sub.2, SnBr.sub.2, SnI.sub.2, and SnCl.sub.2, wherein the second additive includes one of PbI.sub.2, InI.sub.2, and SbI.sub.2.

6. A method for manufacturing a thin-film transistor, the method comprising: forming a gate electrode on a substrate; forming a gate insulating film on an entire face of the substrate including the gate electrode; forming a semiconductor layer on the gate insulating film; and forming a source electrode and a drain electrode on the semiconductor layer so as to be spaced apart from each other, wherein in the forming of the semiconductor layer, the semiconductor layer includes cesium tin triiodide (CsSnI.sub.3) or methylammonium tin triiodide (MASnI.sub.3), wherein the forming of the semiconductor layer includes adding an additive into the semiconductor layer.

7. The method of claim 6, wherein the forming of the semiconductor layer includes forming the semiconductor layer using one selected from spin coating, bar coating, spray, inkjet, flexography, screening, dip-coating, chemical vapor deposition (CVD), atomic layer deposition (ADL), sputtering, thermal evaporation, and gravure.

8. The method of claim 6, wherein in the adding of the additive into the semiconductor layer, the additive is added at a content of 1 mol % to mol % based on the semiconductor layer.

9. The method of claim 8, wherein in the adding of the additive into the semiconductor layer, the additive includes one of SnF.sub.2, SnBr.sub.2, SnI.sub.2, and SnCl.sub.2.

10. The method of claim 8, wherein in the adding of the additive into the semiconductor layer, the additive includes one of PbI.sub.2, InI.sub.2, and SbI.sub.2.

11. The method of claim 8, wherein in the adding of the additive into the semiconductor layer, the additive is a mixture of a first additive and a second additive, wherein the first additive includes one of SnF.sub.2, SnBr.sub.2, SnI.sub.2, and SnCl.sub.2, wherein the second additive includes one of PbI.sub.2, InI.sub.2, and SbI.sub.2.

Description

DESCRIPTION OF THE DRAWINGS

[0025] FIG. 1 is a flowchart showing a manufacturing process of a thin-film transistor according to the present disclosure.

[0026] FIG. 2 is an illustrative view schematically showing a thin-film transistor according to the present disclosure,

[0027] FIG. 3 is a graph showing a structure and a transfer curve of a thin-film transistor according to one embodiment of the present disclosure.

[0028] FIG. 4 is a graph showing a structure and a transfer curve of a thin-film transistor according to another embodiment of the present disclosure.

[0029] FIG. 5 to FIG. 10 are graphs showing change in characteristics due to addition of an additive in a thin-film transistor according to one embodiment of the present disclosure.

Best Mode

[0030] Hereinafter, an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. An embodiment of the present disclosure may be modified in various forms, and the scope of the present disclosure should not be construed as being limited to the following embodiments. This embodiment is provided such that those with average knowledge in the art more completely understands the present disclosure. Therefore, a shape of each of elements in the drawings is exaggerated for clearer descriptions.

[0031] A configuration of the present disclosure for clarifying the solution to the problem to be solved by the present disclosure is described in detail with reference to the accompanying drawings based on a preferred embodiment of the present disclosure. In assigning reference numerals to the components of the drawings, the same reference numerals are allocated to the same components even though they were on different drawings. In the description of the present drawings, components of other drawings may be cited when necessary.

[0032] An example in which a transistor according to the present disclosure has a BGTC (Bottom Gate Top Contact) structure is described. However, the present disclosure is not limited thereto. The transistor according to the present disclosure may have a BGBC (Bottom Gate Bottom Contact) structure.

[0033] FIG. 1 is a flowchart showing a manufacturing process of a thin-film transistor according to the present disclosure, and FIG. 2 is an illustrative diagram schematically illustrating a thin-film transistor according to the present disclosure.

[0034] A bottom type thin-film transistor may be manufactured by providing a substrate, forming a gate electrode on the substrate, forming a gate insulating film on the gate electrode, forming an organic semiconductor layer on the gate insulating film, and forming source/drain electrodes on the organic semiconductor layer so as to be spaced apart from each other.

[0035] Referring to FIG. 1 and FIG. 2, a provided substrate 110 may include a silicon wafer doped with n-type or p-type dopants, a glass substrate, a plastic film made of one selected from a group consisting of polyethersulphone, polyacrylate, polyetherimide, and polyimide, polyethylene terephthalate, and polyethylene naphthalate, or a glass substrate and a plastic film coated with indium tinoxide. However, the present disclosure is not limited thereto.

[0036] A gate electrode 120 may be made of one selected from aluminum (Al), gold (Au), silver (Ag), aluminum alloy (Al-alloy), molybdenum (Mo), molybdenum alloy (Mo-alloy), silver nanowire, gallium indium eutectic, and PEDOT;PSS. The gate electrode may be manufactured via a printing process such as inkjet printing or spraying using ink containing the above materials. Via this printing process, the gate electrode 120 may be formed and thus a vacuum process may be eliminated, so that a manufacturing cost reduction effect may be expected.

[0037] A gate insulating film 130 may be formed on an entire face of the substrate 110 including the gate electrode 120.

[0038] The gate insulating film 130 includes a single film or a multi-layer film of an organic insulating film or an inorganic insulating film, or an organic-inorganic hybrid film. The organic insulating film may include at least one of polymethacrylate (PMMA), polystyrene (PS), phenol-based polymers, acrylic-based polymers, imide-based polymers such as polyimide, arylether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, or parylene. The inorganic insulating film may include one or more selected from a silicon oxide film, a silicon nitride film, Al.sub.2O.sub.3, HfOx, Ta.sub.2O.sub.5, BST, and PZT.

[0039] A semiconductor layer 140 may be formed on an entire face of the gate insulating film 130.

[0040] The semiconductor layer 140 may include cesium tin triiodide (CsSnI.sub.3) or methylammonium tin triiodide (MASnI.sub.3).

[0041] Further, the semiconductor layer 140 may contain at least one additive.

[0042] The additive may be added in an amount of 1 mol % to 30 mol % based on the semiconductor layer.

[0043] In this regard, when the additive is added at a content smaller than 1 mol %, a charge amount reduction effect is insignificant, so that an off current is still high, and thus a low current on/off ratio may occur. To the contrary, when the additive is added in excess of 30 mol %, the additives agglomerate with each other, thereby lowering the charge mobility.

[0044] The additive may include a first additive and a second additive. In this regard, the first additive and the second additive may be added individually or a mixture of the first additive and the second additive may be added.

[0045] In this regard, the first additive may include SnF.sub.2 or any one of SnBr.sub.2, SnI.sub.2, and SnCl.sub.2, and the second additive may include PbI.sub.2, or any one of InI.sub.2, and SbI.sub.2.

[0046] In this regard, Pb contained in the second additive may be added in a trace amount at an environmentally harmless level.

[0047] That is, the additive may include any one of SnF.sub.2, SnBr.sub.2, SnI.sub.2, and SnCl.sub.2, any one of PbI.sub.2, InI.sub.2, and SbI.sub.2, or any one of SnF.sub.2:PbI.sub.2, SnF.sub.2:InI.sub.2, SnF.sub.2:SbI.sub.2, SnBr.sub.2:PbI.sub.2, SnBr.sub.2:InI.sub.2, SnBr.sub.2:SbI.sub.2, SnI.sub.2:PbI.sub.2, SnI.sub.2:InI.sub.2, SnI.sub.2:SbI.sub.2, SnCl.sub.2:PbI.sub.2, SnCl.sub.2:InI.sub.2 and SnCl.sub.2:SbI.sub.2.

[0048] In one example, in accordance with the present disclosure, the first additive and the second additive may be mixed with each other and then a mixture thereof may be added to the semiconductor layer. The first additive may contain Sn and thus may effectively passivate Sn vacancies formed during thin-film formation. The second additive may contain Pb, In or Sb such that the Sn vacancies are substituted with Pb, In or Sb to reduce an amount of the Sn vacancies.

[0049] In this regard, when the mixture of the first additive and the second additive are added thereto, the first additive and the second additive may be mixed with each other at a mixing ratio in a range of 10:90 to 90:10, preferably, 30:70 to 70:30, more preferably, 40:60 to 60:40.

[0050] In one example, the semiconductor layer 140 may be formed by mixing the above material for the semiconductor layer 140 with a solvent such as acetyl-nitrile to prepare a solution and performing a solution process using the solution at room temperature.

[0051] The semiconductor layer 140 may be formed on the gate insulating film 130 using any one selected from spin coating, bar coating, spray, inkjet, flexography, screening, dip-coating, chemical vapor deposition (CVD), atomic layer deposition (ADL), sputtering, thermal evaporation, and gravure. After forming the semiconductor layer 140, heat treatment or optical exposure may be performed thereon to improve element performance such as semiconductor crystallinity and stability.

[0052] In particular, in the transistor according to the present disclosure, the semiconductor layer 140 of an ultra-thin structure may be formed using spin coating or bar coating.

[0053] Further, a thickness of the semiconductor layer 140 may be in a range of 3 nm to 10 nm, and thus transparency thereof may be excellent and may maintain 85 to 90% transparency.

[0054] Further, due to this ultra-thin structure, the semiconductor layer 140 may be applied to a flexible device.

[0055] Further, the source/drain electrodes 151 and 152 may be formed on the semiconductor layer 140 so as to be spaced apart from each other.

[0056] Each of the source/drain electrodes 151 and 152 may be formed as a single layer made of one selected from Au, Al, Ag, Mg, Ca, Yb, Cs-ITO or alloys thereof. In order to improve adhesion thereof with the substrate, each of the source/drain electrodes 151 and 152 may further include an adhesive metal layer made of a metal such as Ti, Cr or Ni and thus may be formed as multiple layers. Alternatively, each of the source/drain electrodes 151 and 152 may be made of graphene, carbon nanotube (CNT), PEDOT:PSS conductive polymer silver nanowire, etc., and thus may be more elastic and flexible than one made of a conventional metal may be. The source/drain electrodes may be manufactured via a printing process such as inkjet printing or spraying using ink containing the above materials. Via this printing process, the source/drain electrodes may be formed and thus the vacuum process may be excluded, so that manufacturing cost reduction may be expected.

[0057] A transistor 100 having the above structure as shown in FIG. 2 may be manufactured.

[0058] Characteristic Measurement

[0059] Hereinafter, with reference to FIG. 5 to FIG. 10, a transfer curve, a current curve (output curve), and characteristics of a thin-film transistor according to an embodiment of the present disclosure are described.

[0060] In each of the semiconductor layer according to one embodiment according to FIG. 3 and the semiconductor layer according to another embodiment according to FIG. 4, a perovskite material was formed on the electrode by dissolving CsI or methylammonium iodide and SnI.sub.2 precursor in DMF or DMSO solution at 0.1 wt % to 50 wt % depending on a thickness of a thin-film to be formed to prepare a solution and then applying the solution on the electrode using spin coating.

[0061] In one example, alternatively, a perovskite material may be formed on the electrode by a vacuum deposition process using thermal evaporation of CsI or methylammonium iodide and the SnI.sub.2 precursor as described above in a vacuum chamber. In the vacuum evaporation, the above additive may be introduced into perovskite via thermal evaporation.

[0062] However, the perovskite-based semiconductor layer for the TFT may be formed using vacuum deposition through thermal evaporation, a solution process (spin coating, bar coating, slot coating, inkjet, dispensing, spray coating, etc.) or a mixed process (two-step process: vacuum deposition and subsequent solution process). However, the present disclosure is not limited to these processes.

[0063] FIG. 3 is a graph showing a structure and a transfer curve of a thin-film transistor according to one embodiment of the present disclosure. FIG. 4 is a graph showing a structure and a transfer curve of a thin-film transistor according to another embodiment of the present disclosure.

[0064] Referring to FIG. 3, in the thin-film transistor according to one embodiment of the present disclosure, the semiconductor layer 140 may include cesium tin triiodide (CsSnI.sub.3) and the aforementioned additive. Referring to FIG. 4, in the thin-film transistor according to one embodiment of the present disclosure, the semiconductor layer 140 may include methylammonium tin triiodide (MASnI.sub.3) and the aforementioned additive.

[0065] FIG. 3B and FIG. 3C are graphs showing a transfer curve of a thin-film transistor according to one embodiment of the present disclosure. The transfer curve represents current I flowing through the semiconductor layer including CsSnI.sub.3 according to application of a gate voltage VG. In this case, a voltage between the source electrode and the drain electrode was set to — 40V (Vds=−40V).

[0066] In this regard, when forming the semiconductor layer, CsI and SnI.sub.2 precursors are dissolved in the DMF or DMSO solution, and then SnF.sub.2 and PbI.sub.2 additives are added thereto. A result as shown in FIG. 3 is identified.

[0067] In this regard, a mixing ratio of the two additives may be 1:2. SnF.sub.2 may be added at 5 mol % and PbI.sub.2 at 10 mol %, based on the semiconductor layer.

[0068] Referring to FIG. 3B and FIG. 3C, it may be identified that the thin-film transistor according to one embodiment of the present disclosure exhibits typical P-type transistor characteristics. In this regard, the mobility is in a range of about 30 to 40 cm.sup.2NS, and the current on/off ratio is greater than or equal to 108. Thus, the thin-film transistor exhibits excellent characteristics.

[0069] FIG. 4B and FIG. 4C are graphs showing a transfer curve of a thin-film transistor according to another embodiment of the present disclosure. The transfer curve represents current I flowing through the semiconductor layer including MASnI.sub.3 according to application of a gate voltage VG. In this case, a voltage between the source electrode and the drain electrode was set to — 40V (Vds=−40V).

[0070] In this regard, when forming the semiconductor layer, MAI and SnI.sub.2 precursors are dissolved in the DMF or DMSO solution, and then SnF.sub.2 and PbI.sub.2 additives are added thereto. A result as shown in FIG. 4 is identified.

[0071] In this regard, a mixing ratio of the two additives may be 1:2. SnF.sub.2 may be added at 5 mol % and PbI.sub.2 at 10 mol %, based on the semiconductor layer.

[0072] Referring to FIG. 4B and FIG. 4C, it may be identified that the thin-film transistor according to one embodiment of the present disclosure exhibits P-type transistor characteristics. In this regard, the mobility is in a range of about 20 to 30 cm.sup.2NS, and the current on/off ratio is greater than or equal to 108. Thus, the thin-film transistor exhibits excellent characteristics.

[0073] FIG. 5 to FIG. 9 are graphs showing change in characteristics due to the addition of the additive in the thin-film transistor according to one embodiment of the present disclosure.

[0074] Specifically, FIG. 5 shows the transfer curves of the MASnI.sub.3 and CsSnI.sub.3 transistors, respectively.

[0075] FIG. 5A shows the transfer curve of the MASnI.sub.3 TFT without the additive. In this case, it may be identified that the TFT exhibits a very low on/off ratio, and thus turn on/off does not occur.

[0076] Further, it may be identified that in the MASnI.sub.3 TFT without the additive, the Sn vacancy may occur during transistor thin-film formation and thus may function as a conductor. According to FIG. 5A, it may be identified that the larger a thickness of the thin-film, the greater a charge amount and thus the larger a current amount.

[0077] FIG. 5B shows the transfer curve of the CsSnI.sub.3 TFT without the additive. As shown in FIG. 5B, it may be identified that in the CsSnI.sub.3 TFT without the additive, the Sn vacancy may occur during transistor thin-film formation and thus may function as a conductor.

[0078] FIG. 6 shows an XRD analysis result (a), a SEM image (b), a SIMS spectrum result (c), a TEM image, a HRTEM image, and a TTF pattern (d) due to additive addition in a thin-film transistor according to one embodiment of the present disclosure.

[0079] First, referring to FIG. 6A, it may be identified that crystallinity is improved when SnF.sub.2 additive is added to the perovskite semiconductor layer (CsSnI.sub.3), and the crystallinity is further improved when a mixture of SnF.sub.2/PbI.sub.2 is added thereto. In other words, it may be identified that the crystallinity improvement is greater when a mixture of the two additives is added thereto.

[0080] Further, referring to FIG. 6B, a resulting structure when each of SnF.sub.2 or SnF.sub.2/PbI.sub.2 is added to the perovskite semiconductor layer (CsSnI.sub.3) may be identified.

[0081] Further, referring to FIG. 6C, it may be identified that the additive SnF.sub.2/PbI.sub.2 is added into the semiconductor layer (CsSnI.sub.3) and is present throughout bulk of a film.

[0082] Further, referring to FIG. 6D, it may be identified that the crystallinity of the semiconductor layer (CsSnI.sub.3) is not significantly affected even when a mixture of the first additive and the second additive is added thereto.

[0083] Further, FIG. 7 shows change (a) in a mobility and a current on/off ratio of a thin-film transistor according to one embodiment of the present disclosure when each of SnF.sub.2, SnBr.sub.2, and SnI.sub.2 additives is added to the semiconductor layer, and a mobility and a current on/off ratio (b) of the thin-film transistor based on a ratio of a Sn content and a Pb content when a mixture of the additives SnF.sub.2 and PbI.sub.2 is added thereto.

[0084] Referring to FIG. 7A, the change in the mobility and the current on/off ratio of the transistor when each of SnF.sub.2, SnBr.sub.2, and SnI.sub.2 additives is added may be identified. Based on a result of the measurement, it may be identified that all three additives improve performance compared to that of one without the additive, and the addition of SnF.sub.2 achieves the greatest performance improvement.

[0085] Further, referring to FIG. 7B, a mobility and a current on/off ratio of the thin-film transistor based on a ratio of a Sn content and a Pb content when a mixture of the additives SnF.sub.2 and PbI.sub.2 as the first additive and the second additive, respectively is added to the semiconductor layer may be identified.

[0086] Further, FIG. 8 shows a transfer curve based on 3, 7, and 11 mol % as a content of SnF.sub.2 as added to the semiconductor layer.

[0087] Referring to FIG. 8, the addition of SnF.sub.2 gradually lowers the off-current, which enables an off-current operation of the transistor.

[0088] However, when the amount of SnF.sub.2 as added exceeds a necessary amount (in one example according to FIG. 7, 11 mol %), the ON current decreases. Thus, it is desirable to properly adjust a content of the additive and add an appropriate amount of the additive thereto (7 mol % in one example according to FIG. 7).

[0089] FIG. 9A shows a transfer curve when SnF.sub.2 alone is added, a transfer curve when PbI alone is added, and a transfer curve when a mixture of SnF.sub.2 and PbI is added.

[0090] Further, FIG. 9B shows a transfer curve when no additive is added, and a transfer curve based on the SnF.sub.2 addition amount when a mixture of SnF.sub.2 and PbI is added.

[0091] In FIG. 9A, it may be identified that when no additive is added to CsSnI.sub.3, that is, when no additive is added, the off current is very high, such that a resulting product does not work as the transistor and acts only as a conductor. That is, a charge amount of CsSnI.sub.3 is very high such that the off current does not occur.

[0092] In this regard, referring to FIG. 9A and FIG. 9B, it may be identified that when a mixture of PbI and SnF is added to CsSnI.sub.3, the off current occurs contrary to the case where no additive is added, and thus a high on/off ratio is achieved.

[0093] When no additive is added, many Sn vacancies may be formed in forming the thin-film made of CsSnI.sub.3 and thus a high charge amount occurs. Thus, the resulting product cannot operate as a transistor and acts only as a conductor.

[0094] On the country, when the mixture of the additives is added, the added Pb and SnF may fill the Sn vacancies, thereby reducing the number of the vacancies such that semiconductor property is achieved.

[0095] When the amount of the added additive is greater than a critical value (for example, 10 mol % of SnF.sub.2 in FIG. 9B), this lowers a charge amount, so that the on current value is lower than a necessary level, which may lower transistor mobility.

[0096] FIG. 10 shows a transfer curve according to the addition of each of (a) SnI.sub.2, (b) SnBr.sub.2, (c) SnCl.sub.2, and (d) SnF.sub.2 to the CsSnI.sub.3 semiconductor thin-film.

[0097] Referring to FIG. 10, it may be identified that when the first additive as a Sn-based additive is added to the CsSnI.sub.3 semiconductor thin-film, the transistor operation is achieved according to the addition of the first additive.

[0098] Referring to FIG. 10, the off-current does not occur when the first additive is not added. However, when an addition amount of the first additive increases, the off-current may decrease. Thus, it may be identified that the charge amount of the semiconductor thin-film is lowered due to the addition of the additive.

[0099] The above detailed description is to illustrate the present disclosure. Further, the foregoing describes a preferred embodiment of the present disclosure, which may be used in a variety of different combinations, variations, and environments. That is, changes or modifications may be made within the scope of the concept of the disclosure disclosed in this specification, within the scope equivalent to the written disclosure and/or within the scope of skill or knowledge in the art. The written embodiment describes the best mode for implementing the technical idea of the present disclosure, and various changes required in the specific application field and use of the present disclosure may be made. Therefore, the above detailed description of the disclosure is not intended to limit the present disclosure to the disclosed embodiments. Further, the appended claims should be construed as including other embodiments.