A memory device is provided. The memory device includes a plurality of memory cells. Each memory cell includes a latch circuit formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The NFETs are formed at a surface of a semiconductor substrate, and the PFETs are disposed at an elevated level over the NFETs.

Provided are oxide semiconductor transistors. The oxide semiconductor transistor includes a substrate, a channel layer arranged on the substrate and having a flat plate shape extending along one plane, a gate electrode facing a part of the channel layer, and a source region and a drain region separated from each other with the gate electrode therebetween, wherein the source region contacts three or more surfaces of the channel layer, and the drain region contacts three or more surfaces of the channel layer.

SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

Provided is a display device having defined therein an opening corresponding to a boundary region, and including a plurality of insulating layers disposed on a base layer, an organic layer disposed in the opening, a first connection electrode disposed on the uppermost insulating layer among the plurality of insulating layers, connected to a first signal line through a first contact hole passing through the organic layer, and connected to a transistor through a second contact hole passing through corresponding insulating layers among the plurality of insulating layers, and a second signal line disposed on a layer different from a layer on which the first line is disposed.

Provided are a thin film transistor capable of minimizing the level of a leakage current and a display apparatus including the same. The thin film transistor includes a buffer layer disposed over a substrate, and a semiconductor layer disposed over the buffer layer, wherein the semiconductor layer includes a first area doped with a first conductivity type and disposed adjacent to an upper surface of the semiconductor layer, a second area spaced apart from the first area, doped with the first conductivity type, and disposed adjacent to the upper surface of the semiconductor layer, a third area doped with a second conductivity type different from the first conductivity type and disposed under the first area, and a fourth area doped with the second conductivity type and disposed under the second area.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

A display substrate, a method for manufacturing the same, and a display device are provided, belonging to the technical field of display. The display substrate includes: a base substrate; a thin film transistor on the base substrate, the thin film transistor including an active layer and a gate electrode on one side of the active layer away from the base substrate, an orthographic projection of the gate electrode on the base substrate at least partially overlapping with an orthographic projection of the active layer on the base substrate; and a conductive pattern arranged on a layer different from the gate electrode, the conductive pattern and the gate electrode being separated by an insulating layer, the orthographic projection of the gate electrode on the base substrate at least partially overlapping with an orthographic projection of the conductive pattern on the base substrate. The technical solution of the present disclosure can improve the yield of OLED display substrates.

The present invention includes a fused polycyclic aromatic compound represented by general formula (1), where in formula (1), one among R.sub.1 and R.sub.2 is represented by general formula (2) and represents a substituent having three to five ring structures, and the other among R.sub.1 and R.sub.2 represents a hydrogen atom, where in formula (2), n represents an integer of 0-2.sub.R. —R.sub.3 represents a divalent linking group obtained by removing two hydrogen atoms from benzene or naphthalene, R.sub.4 represents a divalent linking group obtained by removing two hydrogen atoms from an aromatic ring of an aromatic hydrocarbon, and when n is 2, a plurality of R.sub.4's may be the same as or different from each other, R.sub.5 represents an aromatic hydrocarbon group.

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