Method for manufacturing a substrate comprising a relaxed InGaN layer

Abstract

A method for manufacturing a substrate comprising the following steps of: providing a stack comprising an initial substrate, a GaN layer, a doped InGaN layer and an unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, so as to form a second stack, dipping the second stack and the counter-electrode into an electrolyte solution, and applying a voltage or current between the doped InGaN layer and a counter electrode, to porosify the doped InGaN layer, and relaxing the unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to a support of interest, forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

Claims

1. A process for manufacturing a relaxed epitaxially grown InGaN layer from a GaN/InGaN substrate comprising the following steps of: a) providing a first stack successively comprising an initial substrate, a GaN layer, a doped InGaN layer comprising a first face and a second face, and an unintentionally doped InGaN layer, wherein the first face of the doped InGaN layer faces the GaN layer and the second face of the doped InGaN layer contacts the unintentionally doped InGaN layer, b) transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, the unintentionally doped InGaN layer being in contact with the anodising support so as to form a second stack, and the first face of the doped InGaN layer is accessible to an electrolyte solution, c) connecting the doped InGaN layer and a counter-electrode to a voltage or current generator, d) dipping the second stack and the counter-electrode into the electrolyte solution, such that the first face of the doped InGaN layer contacts the electrolyte solution e) porosifying the doped InGaN layer by applying a voltage or current, between the doped InGaN layer and the counter-electrode to form a doped InGaN layer porosified comprising a first face and a second face, f) transferring the doped InGaN layer porosified and the unintentionally doped InGaN layer to a support of interest to form the GaN/InGaN substrate, wherein a front face of the GaN/InGaN substrate comprises the second face of the doped InGaN layer porosified, g) forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

2. The process according to claim 1, wherein the support of interest comprises a support layer and a buried oxide layer.

3. The process according to claim 2, wherein the support layer is made of sapphire or silicon.

4. The process according to claim 1, wherein the GAN layer is an unintentionally doped GAN layer, and wherein the first stack further comprises a highly doped GaN layer, disposed between the unintentionally doped GaN layer and the doped InGaN layer.

5. The process according to claim 4, wherein step b) is carried out according to the following steps of: electrochemically anodising the highly doped GaN layer to embrittle it, separating the doped InGaN layer and the unintentionally doped InGaN layer from the highly doped GaN layer by thermal activation and/or mechanical action.

6. The process according to claim 4, wherein step b) includes a step in which electrochemical anodization is carried out on the highly doped GaN layer until it dissolves, whereby the doped InGaN layer and the unintentionally doped InGaN layer are separated from the doped GaN layer.

7. The process according to claim 1, wherein step b) is carried out according to a process comprising the following steps of: implanting atomic species to form an embrittlement zone in the doped InGaN layer at a depth close to the final thickness of the layer to be maintained in the final substrate, bonding the first stack to the anodising support, the undoped InGaN layer being in contact with the anodising support, delivering thermal energy to unsecure the doped InGaN layer from the GaN layer in the embrittlement zone.

8. The process according to claim 1, wherein the process includes a subsequent step in which the doped InGaN layer and the unintentionally doped InGaN layer are structured to form InGaN mesas.

9. The process according to claim 8, wherein the doped InGaN layer and the unintentionally doped InGaN layer are structured by photolithography.

10. The process according to claim 8, wherein the process comprises a step in which a doping step by implantation or by metal-organic vapour phase epitaxy is carried out on the InGaN mesas.

11. The process according to claim 10, wherein different doping types are performed during the doping step.

12. The process according to claim 1, wherein the process includes, between step b) and step c), a step during which the doped InGaN layer and the unintentionally doped InGaN layer are structured in order to form InGaN mesas.

13. The process according to claim 12, wherein the doped InGaN layer and the unintentionally doped InGaN layer are structured by photolithography.

14. The process according to claim 12, wherein the process comprises a step, before step c), during which a doping step by implantation or by metal-organic vapour phase epitaxy is carried out on the InGaN mesas.

15. The process according to the claim 14, wherein different doping types are performed during the doping step.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be better understood upon reading the description of exemplary embodiments given purely by way of indicating and in no way limiting purposes, with reference to the appended drawings in which:

(2) FIGS. 1A, 1B, 1C and 1D schematically represent, in a cross-section view, different steps of a process for manufacturing a substrate, comprising an at least partially relaxed InGaN layer, according to a particular embodiment of the invention.

(3) FIGS. 2A, 2B, 2C, 2D and 2E schematically represent, in a cross-section view, different steps of a process for manufacturing a substrate comprising an at least partially relaxed InGaN layer according to a particular embodiment of the invention.

(4) FIG. 3 is a graph representing different phenomena occurring (pre-breakdown, porosification and electropolishing) during an anodisation step, as a function of the doping rate and the potential applied, according to a particular embodiment of the invention.

(5) FIGS. 4A, 4B, 4C, 4D and 4E represent schematically, in a cross-section view, different steps of a process for manufacturing a substrate, comprising an at least partially relaxed InGaN layer, according to a particular embodiment of the invention.

(6) FIG. 5 schematically represents, in a cross-section view, a micro-LED according to a particular embodiment of the invention.

(7) Different parts represented on the figures are not necessarily drawn to a uniform scale, in order to make the figures more legible.

(8) Different possibilities (alternative and embodiments) are to be understood as being not mutually exclusive and being combinable with each other.

(9) Furthermore, in the description hereafter, terms that depend on the orientation, such as “above”, “below”, etc., of a structure apply, by considering that the structure is oriented in the way illustrated in the figures.

DETAILED DISCLOSURE OF PARTICULAR EMBODIMENTS

(10) Although this is by no means limiting, the invention finds applications particularly in the field of colour micro-displays, and more particularly in the manufacture of red green blue pixels. However, it could also be used in the field of photovoltaics or water splitting since, on the one hand, InGaN absorbs in the entire visible spectrum and, on the other hand, its valence and conduction bands are around the water stability range, that are thermodynamic conditions necessary for water decomposition. The invention may also be of interest for the manufacture of LEDs or long wavelength emitting lasers.

(11) The process, making it possible to obtain a substrate or pseudo-substrate, comprising an at least partially relaxed unintentionally doped InGaN layer 14, on a doped InGaN layer 13, comprises a step during which the doped InGaN layer 13 is porosified by electrochemical anodisation.

(12) By partially relaxed, it is meant that the lattice parameter a of the unintentionally doped InGaN layer 14 is greater than the lattice parameter a of the GaN on sapphire layer, allowing more In to be incorporated.

(13) The relaxation percent corresponds to:
Δa/a=(a.sub.c2−a.sub.c1)/a.sub.c1

(14) with a.sub.c1, the lattice parameter of the starting layer, and

(15) a.sub.c2 the lattice parameter of the relaxed layer.

(16) The layer is 100% relaxed if a.sub.c2 corresponds to the lattice parameter of the solid material.

(17) When a.sub.c1=a.sub.c2 the layer is said to be stressed.

(18) By partially relaxed, it is meant a relaxation percent of more than 50%.

(19) More particularly, the process comprise the following steps of:

(20) a) providing a first stack 10 successively comprising an initial substrate 11, a GaN layer 12, a doped InGaN layer 13 and an unintentionally doped InGaN layer 14,

(21) b) transferring the doped InGaN layer 13 and the unintentionally doped InGaN layer 14 to an anodising support 21, the unintentionally doped InGaN layer 14 being in contact with the anodising support 21 so as to form a second stack 20,

(22) c) connecting the doped InGaN layer 13 and a counter-electrode to a voltage or current generator,

(23) d) dipping the second stack 20 and the counter-electrode into an electrolyte solution,

(24) e) applying a voltage or current between the doped InGaN 13 layer and the counter-electrode so as to porosify the doped InGaN layer 13,

(25) f) transferring the doped InGaN layer 13 porosified and the unintentionally doped InGaN layer 14 to a support of interest 31,

(26) g) forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained,

(27) (h) optionally, forming mesas of micrometre size (for example from 1 μm to several tens of micrometres, preferably with a 5 to 10 μm side) to increase the relaxation percent, by relaxing through the free edges of the mesas.

(28) Step h) can be carried out between step b) and step c) or after step g).

(29) FIGS. 1A to 1D are first referred to.

(30) The first stack 10 provided in step a) and represented in FIG. 1A, comprises an initial substrate 11, for example of sapphire, SiC, silicon or glass. Substrate 11 has, for example, a thickness ranging from 350 μm to 1.5 mm.

(31) The GaN layer 12 has, for example, a thickness ranging from 30 nm to 4 μm. The GaN layer is unintentionally doped. By unintentionally doped GaN, it is meant a doping concentration of less than 5.Math.10.sup.17/cm.sup.3.

(32) The doped InGaN layer 13 is n-doped. It has, for example, a thickness ranging from 10 to 200 nm. By doped InGaN, it is meant an electron concentration between 2.Math.10.sup.18 and 2.Math.10.sup.19/cm.sup.3. The doped InGaN layer 101 is electrically conductive. It is porosified in step e).

(33) The doped InGaN layer 13 has two main faces: a first main face 13a and a second main face 13b. The first main face 13a has nitrogen (N) polarity. It is disposed facing the GaN layer 12. The second main face 13b has Gallium (Ga) polarity. It is disposed in contact with the unintentionally doped InGaN layer 14.

(34) The unintentionally doped InGaN layer 14 has preferably a thickness of less than 3 nm, for example 1 nm. By unintentionally doped InGaN, it is meant a doping concentration of less than 5.Math.10.sup.17/cm.sup.3. This layer is electrically insulating. It is not porosified in step e). At the end of step e), the unintentionally doped InGaN layer 14 is non-porous (namely has a porosity of less than 0.01%, preferably less than 0.001%).

(35) Preferably, the first stack 10 consists of the previously mentioned layers. In other words, it does not include any other layers.

(36) These layers are, advantageously, deposited in a full-plate manner on the initial substrate 11.

(37) In step b), the doped InGaN layer 13 and the unintentionally doped InGaN layer 14 are transferred to an anodisation support 21 (FIG. 1B).

(38) The free face of the unintentionally doped InGaN layer 14 is preferably transferred to the oxide layer 23 BOX of the anodising support 21, for example by direct or molecular bonding.

(39) The anodising substrate 21 advantageously comprises a support layer 22 and a so-called BOX (“Buried Oxide layer”) 23, also sometimes referred to as a continuous oxide layer.

(40) The support layer (or support) 22 is, for example, of sapphire, silicon or glass. The support layer 22 has, for example, a thickness ranging from 350 μm to 1.5 mm.

(41) The oxide layer 23 BOX has, for example, a thickness ranging from 100 nm to 4 μm.

(42) According to an advantageous embodiment, this transfer is made using the Smart Cut™ technique. The process includes the following steps of: implanting atomic species to form an embrittlement zone in the doped InGaN layer at a depth close to the final thickness of the layer to be maintained in the final substrate; bonding the first stack 10 to the anodisation support 21, delivering thermal energy to unsecure the doped InGaN layer in the embrittlement zone.

(43) The initial substrate 11 and the unintentionally doped GaN layer 12 of the first stack 10 are detached from the doped InGaN layer 13 by fracturing along the plane of the embrittlement zone. Fracturing is carried out, for example, by heat treatment in a temperature range from 400° C. to 600° C. and for a period of time ranging from a few minutes to a few hours. This fracturing leads to the transfer of the doped InGaN layer 13 and the unintentionally doped InGaN layer 14 to the anodising support 21.

(44) According to a particular embodiment, the initial substrate 11 and the unintentionally doped GaN layer 12 can be detached from the doped InGaN layer 13 by a process of etching a sacrificial intermediate layer, for example with a laser (also known as the “lift off” technique).

(45) At the end of step b), a second stack 20 is thus obtained, successively comprising the support layer 22, the buried oxide layer 23, the unintentionally doped InGaN layer 14, as well as the doped InGaN layer 13 (FIG. 1B). The first face 13a of N polarity is thus accessible.

(46) After implantation of the Smart Cut™, and before the anodisation step, it is possible to perform an Si implantation step to make the doped InGaN layer 13 even more electrically conductive.

(47) According to an alternative embodiment of the process, represented in FIGS. 2A to 2E, the first stack 10 can furthermore comprise a highly doped GaN layer 15, denoted as n++ GaN, between the GaN layer 12 and the doped InGaN layer 13.

(48) The highly doped GaN layer 15 has, for example, a thickness ranging from 10 to 200 nm. By highly doped GaN, it is meant a doping of 10.sup.19/cm.sup.3 or more.

(49) Advantageously, according to this alternative embodiment, after transfer of the first stack 10 to the anodisation support 21 in step b) (FIG. 2B), the highly doped GaN layer 15 is separated from the doped InGaN layer 14 by electrochemically anodising the highly doped GaN layer 15 so as to porosify it (FIG. 2C). The highly doped GaN layer 15 is used as a membrane. The difference in the doping rate results in a high selectivity between porosification and electropolishing (FIG. 3).

(50) Advantageously, separation is facilitated with thermal and/or mechanical activation.

(51) Alternatively, the anodisation step on the doped 15 GaN layer can be carried out prior to the transfer step b), for example if mechanical stress is required to be applied to unsecure the layer.

(52) When the porosification step on the doped GaN layer 15 is carried out before step b), the porosification rate is controlled to keep consistency of the entire stack. After transfer, a thermal and/or mechanical stress is applied to separate the device into two parts, advantageously at the most brittle interface, i.e. between the highly doped GaN layer and the doped InGaN layer.

(53) The step of porosifying the highly doped GaN layer 15 can be performed using the same electrolyte bath (nature and/or concentration) and/or the same voltage (or current applied) as in the step of porosifying the doped InGaN layer 13 (step e).

(54) According to an alternative embodiment represented in FIGS. 4A to 4E, the first stack comprises a highly doped GaN layer 15, disposed between the GaN layer 12 and the doped InGaN layer (FIG. 4A). Step b) is carried out according to the following steps of: connecting the doped GaN layer 15 and a counter-electrode to a voltage or current generator, dipping the first stack 10 and the counter-electrode into an electrolyte solution, applying a voltage or current, between the highly doped GaN layer 15 and the counter-electrode so as to etch the highly doped GaN layer 15, whereby the unintentionally doped InGaN layer 14 and the doped InGaN layer 13 are unsecured from the GaN layer 12 (FIG. 4B).

(55) This results in an InGaN membrane.

(56) The doped InGaN layer 13 and unintentionally doped InGaN layer 14 are then transferred to the anodisation support 21 (step b—FIG. 4C).

(57) In this embodiment, the n++ GaN layer 15 is laterally etched. Advantageously, this embodiment of the process does not implement an additional step to unsecure the InGaN layers 13, 14 from the other layers of the first stack 10. This alternative embodiment is advantageously used for small-size samples (typically up to a few cm.sup.2). For larger areas, electrolyte pathways can be formed beforehand within the doped GaN layer 15.

(58) Following the transfer of the doped InGaN layer 13 and the undoped InGaN layer 14, electrochemical anodisation is carried out on the doped InGaN layer 13. The anodisation can enable the doped InGaN layer 13 to be partially relaxed.

(59) For this, in step c), the second stack 20 and a counter-electrode (CE) 500 are electrically connected to a voltage or current generator. The second stack 20 acts as the working electrode (WE). It will later be referred to as a voltage generator, but it could be a current generator for applying a current between the device and the counter-electrode.

(60) The counter-electrode 500 is made of an electrically conductive material, such as for example a metal like platinum.

(61) In step d), the electrodes are dipped into an electrolyte, also known as an electrolyte bath or electrolyte solution. The electrolyte can be acidic or basic. The electrolyte is, for example, oxalic acid. It can also be KOH, HF, HNO.sub.3 or H.sub.2SO.sub.4.

(62) It is possible to carry out step d) before step c).

(63) In step e), a voltage is applied between the device and the counter-electrode 500. The voltage can range from 1V to 100V, preferably from 3V to 100V. It is applied, for example, for a period of time ranging from a few seconds to a few hours. The anodisation reaction is finished when, at an imposed potential, the current becomes zero: in this case there is no more charge transfer and the electrochemical reaction stops.

(64) The electrochemical anodising step can be carried out under ultraviolet (UV) light. The process can also include a first electrochemical anodisation without adding ultra-violet radiation and a second electrochemical anodisation by adding ultra-violet radiation.

(65) Advantageously, porosification takes place throughout the volume of the doped InGaN layer 13.

(66) At the end of the porosification step, the porosity rate of the doped InGaN layer 13 is at least 1%. It preferably ranges from 5% to 70%.

(67) The largest dimension (the height) of the pores can vary from a few nanometres to a few micrometres. The smallest dimension (the diameter) can vary from a few nanometres to a few hundred nanometres, in particular from 10 nm to 70 nm, for example from 30 nm to 70 nm, and preferably from 15 nm to 40 nm.

(68) The porosification obtained (porosity rate and pore size) depends on the doping of the doped InGaN layer 13 and the process parameters (applied voltage, period of time, nature and concentration of the electrolyte). By varying the porosification, the rate of incorporation/segregation can be controlled. The porosification, and in particular the pore size, can be varied subsequently during the epitaxial regrowth depending on the applied temperature.

(69) The porosification step allows to have a fully or partially relaxed unintentionally doped InGaN layer 14, on an InGaN layer 13 which after porosification is less doped or even no longer doped at all.

(70) To have the second side 13b of metal (Gallium) polarity on the front face, the second stack 20 is transferred onto a support of interest 31, comprising, for example, a support layer 32 preferably of Si, SiC, glass or sapphire, and an oxide layer BOX 33 (step f).

(71) Step f) can be carried out using the SmartCut™ technique, according to the following steps of: implanting atomic species to form an embrittlement zone in the unintentionally doped InGaN layer, at a depth close to the final thickness of the layer to be maintained in the final substrate; bonding the unintentionally doped InGaN layer to the support of interest 31, delivering thermal energy to unsecure the unintentionally doped InGaN layer at the embrittlement zone.

(72) At the end of the process, a substrate 30 of the InGaNOX (“InGaN on substrate X”) type is thus obtained, comprising (FIGS. 1C, 2D, 4D) from the rear face to the front face: a support of interest 31, for example, formed by a support layer 32, preferably of sapphire, and an oxide layer BOX 33, a porosified doped InGaN layer 13, with Ga polarity on the front face, a non-porous at least partially or fully relaxed unintentionally doped InGaN layer 14.

(73) According to an alternative embodiment, the process can include a subsequent step (step h)) in which the porosified InGaN layer and the unintentionally doped InGaN layer are structured to form InGaN mesas (FIG. 1D, 2E, 4E).

(74) According to an advantageous alternative embodiment, the mesas can be formed prior to the porosification step.

(75) The mesas can be structured and then doped. In this alternative embodiment, the process can include, prior to the porosification step, the following steps of: structuring the InGaN layer and the unintentionally doped InGaN layer, which are deposited in a full-plate manner, to form InGaN mesas, advantageously, filling the space between the mesas with an adapted material and planarise the whole thus obtained to have a planar surface, locally implanting a dopant in the mesas at the same or different concentrations; for example, it is possible to perform several implantation operations with different sets of masks.

(76) Alternatively, doping can be performed prior to structuring the mesas. According to this alternative embodiment, the process can include, prior to the porosification step, the following steps of: locally implanting a dopant in the full-plate deposited doped InGaN layer, wherein the dopant concentration can vary along the InGaN layer so as to form more or less doped zones, structuring the InGaN layer and the unintentionally doped InGaN layer, which are full-plate deposited, to form InGaN mesas.

(77) By way of illustration, it is, for example, possible to use a hard mask, such as a SiN or SiO.sub.2 type mask, to carry out the implantation and alignment marks (for example Al, Ti, TiN) to match the mesas to the implanted zones. With two different masks, two zones with different implantation energies can be made, and thus two different doping types in addition to the initial doping of the doped plate, for example by MOCVD. Alignment marks are used to align the two masks for implantation and the mask for mesa etching.

(78) The same set of masks will be used for implantation and mesas.

(79) Structuring the mesas can be done by photolithography.

(80) The mesas, also called elevations, are relief elements. They are obtained, for example, by etching a continuous layer or several superimposed continuous layers, so as to leave only a number of “reliefs” of this layer or these layers. Etching is generally plasma or dry etching (for example RIE plasma). The reliefs make it possible to define pixels.

(81) Preferably, flanks of the mesas are perpendicular to the stack of the different layers of the substrate 30.

(82) The dimensions (width and length) of the mesas range from 500 nm to 500 μm. By width and length, it is meant dimensions parallel to the surface of the underlying stack.

(83) The pitch between two consecutive mesas 100 is from 50 nm to 20 μm.

(84) InGaN mesas comprise a doped InGaN layer 13 and an unintentionally doped InGaN layer 14. Preferably, the mesas consist of these two layers 13, 14.

(85) The doped InGaN layer 13 of the mesas has advantageously a thickness ranging from 10 nm to 200 nm. A layer of a small thickness (less than 100 nm) can contain a high In concentration while maintaining good material quality (few defects). By thickness, it is meant the dimension of the mesa perpendicular to the underlying stack.

(86) Alternatively, doping by implantation can be replaced by doping by metal-organic vapour phase deposition (MOCVD) epitaxy, with Si or Ge doping especially. It is, for example, possible to carry out three successive epitaxy steps to obtain three different doping levels at the end of the process in order to form red, green and blue mesas (RGB).

(87) The process includes a subsequent step in which an epitaxially regrown stack 40 is made either on the full-plate unintentionally doped InGaN layer 14 (FIG. 5) or on the unintentionally doped InGAN layer 14 of the InGaN mesas. This step is advantageously performed to form epitaxially regrown LEDs, in particular all InGaN red (or green) LEDs.

(88) The unintentionally doped InGaN layer 14 is a continuous non-porous 2D layer since it is not porosified during the electrochemical anodisation step. The epitaxially regrown stack 40 is thus facilitated and the epitaxial layer has a better resistance.

(89) The epitaxially regrown stack 40 of an all InGaN LED comprises, for example, successively from the unintentionally doped InGaN layer 14: a n doped InGaN layer 41, preferably with the same In concentration as the InGaN layer of the relaxed substrate, an active zone 42 with one or more red (or green) emitting InGaN/(Ga,In)N quantum wells, a electron barrier 43 based on p doped AlGaN or GaN, a p doped InGaN layer 44, preferably with the same In concentration as the n-InGaN layer or lower, a p++45 doped InGaN layer, preferably with the same In concentration as the p-InGaN layer.

(90) More particularly, an all-InGaN LED structure can successively comprise: an InGaN substrate, a 350 nm n-doped InGaN layer, formed by 15×In.sub.0.03Ga.sub.0.97N/GaN (thicknesses 20 nm/1.8 nm), multiple quantum wells (MQWs), formed by 5×In.sub.0.40Ga.sub.0.60N/In.sub.0.03Ga.sub.0.097N (thicknesses 2.3 nm/5, 7, 11 nm), a uid In.sub.0.03Ga.sub.0.97N layer (10 nm), an Al.sub.0.1Ga.sub.0.9N:Mg layer (20 nm), a Mg-doped In.sub.0.03Ga.sub.0.97N layer (125 nm), a p++ doped In.sub.0.03Ga.sub.0.97N layer (25 nm).

(91) Different growth processes can be used to form epitaxially grown layers.

(92) According to a first alternative embodiment, the regrowth is lateral and a subsequent pixelisation step by etching is advantageously carried out.

(93) According to an alternative embodiment, the regrowth is made vertically above the mesas. In this alternative, the pixels correspond to the underlying mesas.

(94) Advantageously, a passivation layer will be deposited on the flanks of the mesas 100 and/or epitaxially regrown LEDs, for example by atomic layer deposition (ALD). The passivation layer can be of alumina. The passivation layer can have a thickness of a few nanometres, for example from 2 to 5 nm.

REFERENCES

(95) [1] Even et al, “Enhanced In incorporation in full InGaN heterostructure grown on relaxed InGaN pseudo-substrate”, Appl. Phys. Lett. 110, 262103 (2017). [2] Jang et al, “Electrical and structural properties of GaN films and GaN/InGaN light-emitting diodes grown on porous GaN templates fabricated by combined electrochemical and photoelectrochemical etching”, Journal of Alloys and Compounds 589 (2014) 507-512.